EGA Registers

Most register references you will find online are for the VGA exclusively, or else intermingle EGA and VGA to the point where it can be confusing if you are looking for a EGA specific reference.

Every bit listed in this section is specific to the original IBM EGA, unless where noted.

NOTE: The original IBM EGA and several clones have jumpers that can invert address line A09 during port decoding. This causes all the 3XX range registers to be decoded at 2XX. This is a fairly obscure feature and I am not aware of anything that uses it - even video BIOS routines will typically fail to control the card with this jumper set.

The EGA can switch between a port base of 3DX and 3BX for the CRTC and Input Status Register 1 registers - this is primarily for MDA compatibility. The EGA may configure itself this way on boot depending on the status of the EGA DIP Switches.

Indexed Registers

Register indexing is a common way to reduce the complexity of address decoding and conserve the IO address space. In its most common form, it consists of a pair of registers - an address port and a data port. First, a byte address or register index is written to the address port. This selects the desired register, assuming it represents a valid index. Then, with the desired register selected, the new value for the register is written to the data port. The address port and data port are typically consecutive IO addresses, with the address port at an even address. There is a good reason for this.

A consequence of the 8088’s transparent 8-bit bus is that an indexed register can be selected and written to via a single word-sized OUT. The data byte is typically packed into AH, with the address in AL. The 8088’s BIU will convert the word write into two 8-bit writes at the base IO address and then the base address + 1. On the AT and subsequent 16-bit architectures, this conversion had to be specifically emulated by hardware on the motherboard.

Indexed registers can also be implemented via an internal flip-flop, where only a single IO port is required. The first write will set the register index, the second write will set the corresponding register data. Under this scheme there must be a way to reset the flip-flop to a known state. This technique is used for the EGA’s single Attribute Controller IO port, which can be reset by reading Input Status Register 1 at either 3DAh or 3BAh, depending on the EGA’s current base address.

Register File Overview

Register Set Details Index

• External Registers
• CRTC
• Attribute Controller

CRTC Registers

The EGA uses a custom LSI CRTC chip. It is very similar in operation to the Motorola 6845, but defines most vertical counters in units of scanlines. Using scanlines as the vertical unit is more convenient for a graphics-mode oriented video adapter. It also has the big advantage of not requiring any memory-addressing tricks that lead to inconvenient video memory layouts on the CGA and Hercules cards.

Most of the EGA CRTC registers are write-only, with the exception of the three register pairs that hold memory addresses - the Start Address, Cursor Location, and Light Pen address registers can be read out. The inability to read the EGA CRTC registers was an annoyance for graphics and games programmers everywhere. This was rectified on the VGA which made most of the register file readable, but much software written for 4bpp modes did not rely on this to maintain backwards compatibility.

Graphics Controller Registers

On the original IBM EGA, there are two separate Graphics Controller chips. They can generally be treated as a single entity except for the two Graphics Position registers. These two registers are used to tell each of the graphics controllers which pair of graphics planes they will be managing.

The Graphics Controller chips lack an IOW pin, thus all their registers are write-only.

Graphics Controller Indexed Registers

Sequencer Registers

Sequencer Indexed Registers

Attribute Controller Registers

Attribute Controller Indexed Registers

The first sixteen registers in the Attribute Controller define a 4bpp palette.

External Register Details

Attribute Controller Register Details