Introduction

Welcome to “The PC Emulation Book.”

This document aims to become a comprehensive guide to emulating the original models of the IBM Personal Computer:

• The IBM Model 5150 Personal Computer
• The IBM Model 5160 Personal Computer XT

When we refer to the original “IBM PC”, we are technically referring to the IBM Model 5150. However, the slightly improved IBM Model 5160 (otherwise known as the IBM XT) is similar enough in design and function that they are often lumped together. In this book, we will refer to the XT when a distinction between the PC and XT is important. Otherwise, consider any reference to the “PC” as referring to either model.

🚧 UNDER CONSTRUCTION! 🚧

You’ll notice that many of the pages in this book are empty stubs. Content is still being fleshed out. Here is a list of some of the more complete pages:

• The Intel 8253 Programmable Interval Timer
• The Intel 8259 Programmable Interrupt Controller
• The Keyboard
• The Keyboard Interface
• Display Concepts

Additionally, many of the appendices contain useful reference information:

• ASCII Table
• BIOS Data Area
• BIOS Interrupts
• BIOS VIdoe Modes
• IO Ports

Why Emulate the PC?

The IBM PC is arguably one of the most influential computers in history, establishing standards that enabled the proliferation of “PC-compatible” systems and cemented the very term “PC” as an Intel-based system, probably running a Microsoft operating system. The “PC” lives on even today, only recently challenged for supremacy by the rise of ARM-based CPUs.

The PC was an open and well-documented system. IBM published full schematics and commented BIOS source code listings, allowing anyone to understand in great detail how the system operated, even without owning the physical hardware.

There are thousands of software titles to explore on a PC emulator, although the PC’s limited graphics and sound capabilities make many of the games for the platform less than spectacular. Still, there are some classic titles that are still fun to play today, such as AlleyCat and Digger.

If you’re up for a challenge, recently several demos have been released that push the original PC hardware to its utter limits and require cycle-exact emulation of the 5150 and its components. These demos include 8088 MPH, released in 2015, and Area 5150, released in 2022.

Even without any attempt at cycle-accuracy, the PC can be emulated with a respectable level of compatibility.

What You’ll Learn

This book aims to cover the complete process of building a PC emulator from the ground up, including:

• Hardware Architecture: Understanding the IBM PC’s system design and component interactions
• CPU Emulation: Implementing the Intel 8088 processor
• Support Chips: Emulating the various Intel support chips that made the PC work
• Peripheral Devices: Implementing keyboards, displays, storage, and other I/O devices
• System Integration: Bringing all components together into a working emulator

Target Audience

This book is intended for emulator authors, but retro-developers may find it a useful reference as well, or anyone simply curious about how classic computers of the era worked.

Prerequisites

To get the most out of this book, you should have:

• A basic understanding of computer architecture concepts
• Familiarity with a high-performance programming language (C, C++, Rust, or similar)
• Basic electronics knowledge
  • This is minimal, but you should understand the concepts of voltage, the function of resistors, and what a tri-state output is. If you need it, a refresher can be found in the appendices: Electronics Concepts.
• Basic understanding of digital logic
• Some experience with emulation
  • If you have never programmed an emulator before, it is recommended that you start with the CHIP-8, a simple system that teaches basic emulation concepts. You can find a guide here.

License

This book is open-source and all content is licensed under the Creative Commons CC BY 4.0 license, except where otherwise noted. See LICENSE.

Acknowledgements

Several resources have been invaluable references in both my development of my emulator and in curating material for this book. I would like to thank the following for graciously providing permission to directly adapt or include their work:

• modem7 of minuszerodegrees.net
• Scott Smitelli of cosmodoc.org
• Francis Gulotta of roborooter.com

Other invaluable resources for PC information include:

• John Elliott’s seasip.org
• Ken Shirriff’s blog at righto.org
• Reenigne’s blog at reenigne.org
• Great Heirophant’s blog at nerdlypleasures.blogspot.com
• VileR’s int10h.org

Contributing

The main source repository for the PC Emulation Book can be found here. PRs are welcome.

AI Policy

The PC Emulation Book strives to maintain accurate and authentically voiced information. To that end, all content contributed to the PC Emulation book should be written by human beings. Don’t worry if English is not your first language - I will be glad to perform editorial duties for you.

IBM PC/XT Architecture Overview

The design of the original IBM 5150 reflected IBM’s project requirements to create a low-cost, maintainable system largely comprised of off-the-shelf parts, yet capable of being expanded. They succeeded in that effort far beyond any conceivable expectations - the IBM PC is now recognized as the ancestor of a line of “PC Compatible” systems that continue to be sold to this day.

CPU

IBM chose the Intel 8088 for the 5150, which is also used in the 5160. The 8088 was a lower-cost variant of the 8086 CPU. While still 16-bit internally, the 8088 only had an 8-bit data bus. This simplified the PC’s motherboard design, and made it easy to build a system around Intel’s various 8-bit peripheral chips.

The 8088 has 20 address lines, allowing it to address \(2^{20}\) bytes, or 1MB.

IBM chose to reserve addresses above 0xA0000, leading to the infamous “640KiB” memory limit that is often mistakenly blamed on Microsoft.

Memory

Depending on the model and revision, the PC could be fitted with up to 256K of RAM on the motherboard. Memory expansion cards to bring a system up to the maximum 640KiB were quite commonplace in the latter years of the PC’s life. Multi-function cards provided RAM upgrades along with extra peripherals such as printer, serial, and game ports.

The memory used in the PC is common dynamic RAM (DRAM). The PC lacks dedicated refresh circuitry to maintain the contents of DRAM, and must use some of its accessory hardware to perform this task. The process of DRAM refresh makes the entire system approximately 6% slower.

Timer

The PC contains an Intel 8253 Programmable Interrupt Timer with three timing channels.

Timer Channel 0

The first channel, 0, is dedicated to maintaining the system clock via the BIOS. The PC has no real-time clock or battery-backup, so the date and time must be entered when booting the system. The time-of-day clock is maintained in software, and was notoriously inaccurate. For these reasons, real-time clock modules were popular upgrades, often found on multi-function cards. Timer channel 0 is connected to IRQ0 and is the only channel that can generate *timer interrupts.

Timer Channel 1

The second channel, 1, is dedicated to the operation of refreshing the system’s DRAM and generally cannot be used by programs.

Timer Channel 2

The third channel, 2, is the only channel connected to the PC Speaker. Programming this channel allows sounds to be played, but it can also be used as a general timing facility.

DMA

The PC has an Intel 8237 Direct Memory Access Controller. DMA is a method by which expansion cards can read and write to memory without needing the CPU to participate in the transfer, which can make timing-critical operations such as floppy-disk access more reliable, especially if the CPU is busy. DMA was used to operate the PC’s floppy drives, and was often used by add-on hard disk controllers. The PC has three DMA channels, one of which is dedicated to the process of DRAM refresh, leaving only two available.

Interrupts

The PC has an Intel 8259 Programmable Interrupt Controller with 8 interrupt lines. Interrupts are a way for components of a hardware system to request attention from the CPU.

Expansion Bus

The 8-bit data bus of the 8088 would also dictate the 8-bit data width of the system’s expansion bus. This bus would later be expanded to 16-bits with the IBM 5170 AT, and would later be dubbed the ISA bus by Compaq¹ and a growing consortium of PC clone manufacturers.

System Crystal

The 5150 has a single main system crystal with a frequency of 14.31818MHz. This frequency is exactly four times the NTSC color subcarrier frequency.

The crystal frequency can be expressed as a fraction:

$$f_{crystal} = \frac{315}{22} \text{ MHz} = 14.31818\overline{18} \text{ MHz}$$

This choice was likely made due to the low cost of NTSC-derived clock crystals, as they were being manufactured by the millions to be used in television sets. It also made the PC more easily compatible with North American television sets, making low-cost display option available to PC owners. It also allowed the IBM Color Graphics Adapter to omit a separate crystal.

CPU Clock

The CPU frequency of 4.77 MHz is obtained by dividing the system clock by 3:

$$\frac{14.3181818}{3} = 4.773\text{ MHz}$$

The 8088 was rated for 5MHz operation², so this represents about a 5% underclock.

The PC vs XT

The IBM model 5160 (XT) is very similar to the model 5150 PC, with a few differences:

• Eight expansion slots vs the PC’s five
• The minimum installed RAM was increased to 128K
• The underutilized cassette interface port was dropped
• Slight changes to DRAM refresh logic
• ROM chip size was increased from 8K to 32K
• A larger, 130W power supply to accommodate hard drives

References

1. wikipedia.org Industry Standard Architecture. ↩

2. Intel Corporation. 8088 8-Bit Hmos Microprocessor. Intel Corporation, August 1990. Document Number: 231456-006. Available at: Intel 8088 Data Sheet PDF ↩

Intel 8259 Programmable Interrupt Controller

The Intel 8259 Programmable Interrupt Controller (PIC) plays an essential role in the operation of much of the hardware of the IBM PC. The PIC can be thought of as an expansion unit to the 8088’s single INTR pin, allowing 8 separate interrupt sources to be handled in a prioritized manner.

The PIC is a surprisingly challenging chip to emulate correctly, partially due to some ambiguities in its documentation.

Overview

The 8 inputs of the PIC are called Interrupt Request lines, which are often referred to as IRQs (Interrupt reQuest).

The PIC has three main 8-bit registers. Each bit in these registers corresponds to an IRQ with the least significant bit mapping to IRQ 0 and the most significant bit mapping to IRQ 7.

• Interrupt Request Register (IRR): This register holds bits reflecting the IRQ lines that are requesting service.
• Interrupt Mask Register (IMR): A 1 bit set in this register prevents the corresponding IRQ line from being serviced.
• In-Service Register (ISR): A 1 bit set in this register indicates that the corresponding IRQ has been acknowledged by the CPU and is now “in-service”.

The 8 IRQs of the PIC are ordered in terms of priority, with IRQ 0 being the highest priority, and IRQ 7 being the lowest priority. This means that if IRQ 0 and IRQ 1 occur simultaneously, IRQ 0 will be serviced first.

This also means that it is possible for a higher priority interrupt to be serviced while a lower priority interrupt is already in service. Normally, the 8088 clears the I flag when executing an interrupt. If a programmer desires their interrupt service routine to be reentrant, they would need to issue an STI instruction to allow this to occur.

IBM PC PIC Configuration

IRQ Assignments

The IBM PC maps devices to the 8259’s IRQ lines as follows. Some of these connections are direct traces on the motherboard, other IRQs are connected to the ISA bus. In some cases, a peripheral card may have had a jumper to allow selection of a particular IRQ.

I/O Ports

The 8259 has a single address pin, A0, via which one of two registers can be selected. The two registers are decoded by the PC at the following addresses:

The Unimportant Stuff

The 8259 was designed to be compatible not only with the 8088 and 8086, but with Intel’s earlier CPUs, the 8080 and 8085. There are various mode flag bits that control whether the 8259 should expect to be paired with an 8088 or not - obviously, on the IBM PC, you can expect these bits to be set properly, and emulation of the 8080 modes is certainly not required.

The 8259 supported daisy-chaining of additional 8259 chips to enable more interrupt sources to be handled - something that Intel called cascading. This was not used on the IBM PC, which only had a single 8259. Two 8259s were employed on the IBM 5170 AT in a primary/secondary configuration. Obviously this is something you do not need to emulate either.

The PIC can be operated in edge-triggered or level-triggered mode. The IBM PC exclusively operates in edge-triggered mode, but implementing level-triggered mode is fairly trivial to do.

There are additional features like priority rotation and special mask mode which are not used by the IBM PC.

Interrupt Processing Logic

The important thing to understand about the PIC is that it is implemented as an array of 8 priority cell circuits. The IRR, IMR, and ISR “registers” are simply latches within each priority cell. This means that a good part of the interrupt evaluation logic happens continuously, since it is simply driven by immediate state of the circuit. The PIC has no clock input, so all it can do is respond to changes of its input pins. With one exception - but we’ll talk about that later.

Let’s look at an example of interrupt logic flow:

The Simple Version

1. A device raises its IRQ line connected to the PIC.
2. The PIC looks to see if that IRQ is masked off in the IMR, if it is already in service, or if a higher-priority interrupt is in service, in which case the interrupt cannot be serviced at the moment.
3. If the IRQ can be serviced, the PIC raises the INTR line to the CPU.
4. The CPU acknowledges the interrupt and the PIC sets the corresponding bit in the ISR to indicate that the interrupt is now in service. The corresponding bit in the IRR is cleared to indicate the IRQ is no longer requesting service.
5. The CPU executes the interrupt based on the 8-bit vector the PIC provides in response to the CPU’s interrupt acknowledgement.
6. The interrupt service routine executes. When it is done, it sends an End-of-Interrupt (EOI) command to the PIC.
7. The PIC clears the corresponding bit in the ISR indicating that the interrupt has completed servicing.

The original IRQ line may remain high at this point, but in the PC’s standard edge-triggered mode it will not be serviced again until it transitions low and then high again.

The Detailed Version

1. A device raises its IRQ line connected to the PIC.
2. The low-to-high transition of the IRQ line sets the IRQ’s edge latch and sets the corresponding bit in the IRR.
   1. If the corresponding bit in the IMR is set, the signal from the IRR does not propagate further.
   2. If the corresponding bit in the IMR is clear, the signal from the IRR reaches the Priority Resolver.
3. The priority resolver checks to see if the corresponding bit in the ISR is set, or if any bits lower than the corresponding bit are set, indicating a higher priority interrupt is already in service.
   1. If any of these bits are set, nothing further happens for the moment.
   2. If none of these bits are set, the priority resolver will instruct the control logic to raise the PIC’s INTR pin, which is connected to the CPU.
4. The CPU finishes an instruction, at which point it samples the INTR pin.
5. The CPU notices INTR is high.
   1. If the CPU’s I flag is cleared, it ignores INTR being high and continues execution as normal.
6. The CPU begins to acknowledge the interrupt.
   1. The CPU issues one bus cycle with the INTA bus status encoded.
   2. The CPU bus controller decodes the INTA bus status and asserts the physical \(\overline{INTA}\) pin.
7. The PIC detects the \(\overline{INTA}\) pin going high.
   1. The priority resolver sets the highest-priority bit in the ISR to indicate that the interrupt is entering service.
   2. In edge-triggered mode, the priority resolver clears the corresponding bit in the IRR.
   • This is the only difference between edge-triggered mode and level-triggered mode.
   3. The control logic asserts the internal \(\overline{FREEZE}\) signal. This prevents any change to any bit in the IRR while the interrupt acknowledge process is active.
8. The \(\overline{INTA}\) pin goes low as the CPU completes the INTA bus cycle.
9. The \(\overline{INTA}\) pin goes high again as the CPU issues a second INTA bus cycle.
10. The PIC emits the 8-bit interrupt vector which the CPU reads during the second INTA bus cycle.
11. The \(\overline{INTA}\) pin goes low as the CPU completes the second INTA bus cycle.
    1. The control logic de-asserts the \(\overline{FREEZE}\) signal, allowing the IRR to update again.
    2. In auto-EOI mode, the priority resolver clears the corresponding ISR bit.
12. The CPU uses the interrupt vector received from the PIC to look up a far pointer to the correct Interrupt Service Routine from the Interrupt Vector Table.
13. The CPU clears the I and T flags, then jumps to the interrupt service routine.
14. At the end of the interrupt service routine, the routine sends an EOI command to the PIC.
15. The PIC clears the appropriate bit in the ISR to indicate that the interrupt has completed servicing.

The Intel 8253 Programmable Interval Timer

The 8253 Programmable Interval Timer (PIT) is responsible for a number of tasks on the IBM PC. It maintains the system time, drives DRAM refresh, and controls the PC speaker to generate sound.

Overview

The PIT contains three independently operating 16-bit counters or ‘channels’, each capable of operating in different modes.

Physically, each timer channel is assigned a clock input, a gate pin, and an output pin (OUT). The gate pin can be used to control or disable counting in specific modes.

Counters are operated by first configuring them by writing a Control Word to the 8253’s Control Word Register. Then, an initial count - often referred to as a ‘reload value’ - is written directly to the timer channel port. A counter has a full 16-bit range, as an initial count of 0 is treated as a count of 65,536 in binary mode or \(10^4\) in BCD mode.

Once configured and running, on each tick of the channel’s clock input, the channel’s internal Counting Element decrements. When the counter reaches 0 (or 1 in some modes), some specific behavior will be triggered (depending on mode), usually changing the state of the channel’s output pin.

The current value of a counter channel can be read at any time by reading from the channel’s specified port.

Pinout

Figure 1: Intel 8253 Pinout

The 8253 has an 8-bit data bus by which you read and write the chip’s registers, which are selected by the A0 and A1 pins.

IBM PC Timer Configuration

The 8253 has three independent clock input pins, allowing each counter to be driven at a different frequency. The IBM PC ties all three clock inputs to the same clock line, which runs at the system crystal frequency divided by 12.

$$f_{timer} = \frac{\frac{315}{22}}{12} \text{ MHz} = 1.19318\overline{18} \text{ MHz}$$

Note: Other systems that use the 8253 can connect these timer clock inputs in different ways - even connecting one timer channel output to the clock input of another to act as a clock divisor.

Timer 0

Timer 0’s OUT pin is directly connected to the IR0 pin of the 8259A Programmable Interrupt Controller. When the Timer 0 OUT pin has a low-to-high transition, this will trigger an IRQ0. This causes an interrupt 8, which normally is configured to maintain the system’s time of day clock by the BIOS.

The BIOS initializes Timer 0 to a reload value of 0 (65,536)

$$ T = \frac{65536}{1.19318\overline{18}\times 10^{6}} \approx 0.0549254\ \text{s} $$

$$ T \approx 54.93\ \text{ms} $$

$$ \frac{1\text{s}}{54.93\text{ms}} \approx 18.2Hz $$

This will cause an Interrupt 8 to execute 18.2 times per second.

Many applications, especially games, will use Timer 0 for their own purposes, and so the time of day clock was notoriously inaccurate without being synchronized to a realtime clock module.

Timer 0’s GATE pin is tied to +5v.

Timer 1

Timer 1’s OUT pin connects to a 74LS74 flip-flop which latches its output. The output of this flip flop is connected to the DRQ0 pin of the 8237 DMA Controller, and is reset by the \(\overline{\text{DACK0}}\) signal. This causes one DMA transfer to occur in read mode, which refreshes the system’s DRAM.

The BIOS initializes Timer 1 to a reload value of 18:

$$ T = \frac{18}{1.19318\overline{18}\times 10^{6}} \approx 0.0000151\ \text{s} $$

$$ T \approx 15.1\ \text{μs} $$

$$ \frac{1\text{s}}{15.1\times 10^{-6}\text{s}} \approx 66.2\text{KHz} $$

This will cause a DMA refresh request approximately every 15 microseconds, or every 72 clock cycles. If this sounds like a lot, it is. The DRAM refresh process robs the 8088 of about 5-6% of its performance, depending on bus activity.

Note: You can ignore this channel if you are not interested in cycle-accuracy. However, the IBM PC BIOS does check that Timer 1 is running by checking that the DMA channel 0 is counting. You can hack your way around this test by just making the DMA channel 0 count on read.

Timer 1’s GATE pin is tied to +5v.

Timer 2

Timer 2’s OUT pin connects to the PC’s speaker and cassette interface circuitry. Timer 2 is typically configured to produce square waves to drive the speaker to play notes of specific frequencies, and Timer 2’s GATE input can be used to silence the speaker when desired.

For more details, see the PC Speaker chapter.

Timer 2’s GATE pin is tied to the 8255 PPI’s Port B, Bit 0 (Pin #18).

I/O Ports

The 8253 has two address lines, A0 and A1, which allow selection of four ports. These four ports are decoded by the PC at the following addresses:

Control Word Format

The 8253’s control word can be written to at port 0x43 and is used to configure one of the three counters, each of which can be configured with different modes.

Figure 2: Intel 8253 Control Word Format

The specified channel’s counting mode, IO mode, and whether or not it should count in BCD, is configured with a single 8-bit write. Note that using 0b11 as the timer selection is invalid on the 8253. On the 8254, it selects the read-back command, which will not be covered here.

Counter Channel Configuration

Binary vs BCD Mode

A timer channel can be configured to count in either binary or Binary Coded Decimal (BCD) mode. I have not seen any software that actually uses BCD mode. When writing your initial 8253 implementation, you can probably ignore BCD mode.

RW Mode

A timer channel can be configured for 16-bit read/writes in LSBMSB mode using 0b11 in the RW field, or in one of two 8-bit read/write modes:

• LSB (0b01):
  • On write, an 8-bit value is used to initialize the \(\text{CR}_l\) register, which holds the least significant 8 bits of the initial 16-bit count.
  • On read, the contents of the \(\text{O}_l\) register are returned. See Counter Channel Operation.
• MSB (0b10):
  • On write, an 8-bit value is used to initialize the \(\text{CR}_m\) register, which holds the most significant 8 bits of the initial 16-bit count.
  • On read, the contents of the \(\text{O}_m\) register are returned. See Counter Channel Operation.

The 8-bit RW modes allow programming a timer channel with fewer writes. In MSB mode, the full range of a timer channel is available, with reduced granularity.

Note: The RW mode of a channel does not affect its basic counting operation. It remains a full 16-bit counter internally regardless of input mode.

In LSBMSB mode, it takes two 8-bit writes to read or write to the timer channel. An internal latch keeps track of whether the initial LSB has been written. On a write, the first byte written is used to initialize the \(\text{CR}_l\) register. The second byte initializes the \(\text{CR}_m\) register. On a read, the first read returns the \(\text{O}_l\) register, the second read returns the \(\text{O}_m\) register.

Warning: The 8253 cannot handle interleaved 16-bit read and write operations. In LSBMSB mode if you write one byte and then read one byte without completing the write operation, you will receive random data. Some software has been observed improperly operating the 8253 in this way, especially software designed for the 8254 which did not have this limitation. Ensure that your 8253 can recover in this scenario - what value you decide to return is up to you - the actual value is nondeterministic “open bus” behavior internal to the chip.

Counter Latch Command

There is a small matter of concern when a channel is configured for LSBMSB mode. Since it takes two bytes to read the full 16-bit counter value, it is possible that the counter can decrement between the time the first byte is read and the second. Therefore, a Counter Latch command is provided. The Counter Latch command is sent by setting the RW field of the control word to 0b00. This does not change the counter channel’s configuration otherwise - the Mode and BCD bits are ignored when sending the counter latch command. See the Counter Latch Operation section below for how the latching is implemented.

Counter Channel Operation

Figure 3: Intel 8253 Counter Block Diagram

There are a few important things to note in the channel block diagram above. The heart of the counter is the Counting Element (CE). This is a 16-bit synchronous down-counter that contains the current count value. Above the CE are \(\text{CR}_m\) and \(\text{CR}_l\), two halves of the Count Register (CR). The CR holds the initially configured count, and is used to reload the CE on terminal count in modes that do so.

The count value is transferred from the CR to the CE when a full write of the CR is complete. This may require one or two bytes, depending on the configured RW Mode.

Both Count Registers are initialized to 0 whenever a channel’s mode is set. This avoids leaving either of the CR registers in an indeterminate state when using either byte RW mode.

Counter Loading

Counter loading is not instantaneous on write. A CR is not loaded until the 8253 sees a full clock cycle with a rising and falling edge after the write occurs. If the specific mode requires that the CE be loaded immediately from the CR, all 16-bits are transferred at once.

A count can be loaded with any 16-bit value from 0-65,535. To allow a full 16-bit range, a count value of 0 is interpreted by the 8253 as a count value of 65536.

Counter Latch Operation

Below the CE are \(\text{O}_m\) and \(\text{O}_l\), two halves of the Output Latch. When reading the count value from a channel, we are actually reading from the output latch. Typically, the output latch is updated each time the CE changes. When the Counter Latch Command is issued, the CE simply stops updating the Output Latch, essentially “freezing” the value inside at the point in which the latch command was issued.

When the Output Latch is fully read, which may take one or two bytes depending on the configured RW Mode, the Output Latch is “unfrozen” and will resume being updated by the CE on every tick.

The Output Latch operation can only be reset by fully reading the Output Latch. Issuing a new Counter Latch command will be ignored until the Output Latch is fully read.

Clocking Logic

An 8253 timer channel generally takes an action, such as transferring the CR to CE or decrementing the CE on the next falling edge of its input clock.

Counter Operating Modes

Timer channels can be set to any of 6 different modes.

• Mode 0: Interrupt on Terminal Count
• Mode 1: Hardware Retriggerable One-Shot
• Mode 2: Rate Generator
• Mode 3: Square Wave Generator
• Mode 4: Software Triggered Strobe
• Mode 5: Hardware Triggered Strobe (Retriggerable)

Mode 0 — Interrupt on Terminal Count

Upon setting this mode, OUT is initially LOW. This is the only mode where the initial OUT state is LOW after a mode is set.

In Mode 0, the counter counts down once per tick from the initial count until it reaches 0. When it reaches 0, OUT goes high and stays high until reprogrammed. The counter will continue to count, rolling over from 0 to 0xFFFF, but no longer affects the state of the OUT pin.

Note: The word “Interrupt” in this mode name can be a little misleading. Nothing about this mode is specific to generating interrupts. Interrupts are generated whenever timer channel 0’s output has a rising edge. Therefore, any operating mode can generate interrupts with timer channel 0. Additionally, using the Interrupt on Terminal Count mode on any other timer channel will not generate an interrupt.

Count Loading

• After setting the mode and initial count, the CR will be loaded into the CE on the next clock edge after the final write of the initial count.

Output Behavior

• After mode set: OUT → LOW
• When countdown reaches 0: OUT → HIGH (and remains HIGH)
• Upon writing new count: OUT → LOW

GATE Behavior

• Level-triggered
• GATE HIGH: enables counting
• GATE LOW: inhibits counting (freezes the countdown)

Reload Behavior

• In 8-bit RW modes:
  • Writing either the LSB or MSB while the counter is running forces OUT low immediately.
  • The CR will be loaded into the CE on the next clock edge.
• In LSBMSB RW mode:
  • Writing the LSB while the counter is running disables counting and forces OUT low immediately.
  • Writing the MSB will load the CR into the CE on the next clock edge.

Timing

• For initial count = N, OUT will go high up to N+1 timer clock cycles after the write.

Figure 4: Timer Mode 0 - Interrupt on Terminal Count Timing

Mode 1 — Hardware Retriggerable One-Shot

Summary

This mode allows a low pulse of the OUT pin of a configurable length, triggerable via the GATE pin. This mode is inoperable on the IBM PC except on timer channel 2.

Upon setting this mode, OUT is initially HIGH. A rising edge of the GATE input will trigger OUT → LOW on the next clock edge. When the count reaches 0, OUT → HIGH. The counter will continue to count, rolling over from 0 to 0xFFFF, but will not affect the state of the OUT pin until the counter is re-triggered.

We refer to a “trigger” as a LOW → HIGH transition of the GATE pin.

Note: The count starts running as soon as Mode 1 is selected - but you’ll note that the CE is not loaded until a GATE trigger. Presumably, the counting element still contains whatever it had in it when the mode was set, but this has not been verified.

Count Loading

• After setting the mode and initial count, the CR will hold the initial count but will NOT write it into the CE until a trigger occurs.

Output Behavior

• After mode set: OUT → HIGH
• After GATE LOW → HIGH: OUT → LOW
• At terminal count: OUT → HIGH

GATE Behavior

• Edge-triggered
• GATE LOW -> HIGH: Trigger. The CR is loaded into the CE on the next clock edge.
  • Since the trigger reloads the CE, another trigger will restart any count in progress.

Reload Behavior

• Writing a new count during an active count will not affect the current count until the next trigger, as the trigger controls loading of the CE from CR.

Timing

Figure 5: Timer Mode 1 - Hardware Retriggerable One-Shot Timing

Mode 2 — Rate Generator

Summary

In this mode, OUT normally remains HIGH, but produces regular one-clock-wide low pulses. This mode is useful when a periodic LOW → HIGH transition is required.

On the IBM PC, timer channel 1 is typically configured for Mode 2 to repeatedly generate the \(DREQ0\) signal.

Output Behavior

• After mode set: OUT → HIGH
• When count reaches 1: OUT → LOW
• When count reaches 0: OUT → HIGH

GATE Behavior

• Edge-triggered
• GATE LOW -> HIGH: Trigger. The CR is loaded into the CE on the next clock edge. Counting enabled.
• GATE LOW: OUT is forced HIGH, counting disabled.

Reload Behavior

• Writing a new count during an active count will not affect the current count until either a terminal count or a GATE trigger.
• CR is automatically loaded into the CE after terminal count is reached, restarting the count.

Constraints

• A count of 1 is invalid and will cause the timer channel not to function.

Timing

Figure 5: Timer Mode 2 - Rate Generator Timing

Mode 3 — Square Wave Generator

Summary

Similar to Mode 2, but produces a square wave: OUT alternates high and low with a 50% duty cycle (if the initial count is even). This is a general-purpose mode with many applications. The IBM BIOS sets timer channel 0 to Mode 3 to run the BIOS time-of-day clock. This mode can also be used to drive a tone of a specific frequency to the PC speaker on timer channel 2.

This mode is a bit more complex than the other modes. The 8253 creates a square wave of a period determined by the initial count by decrementing the counting element by 2 instead of 1. This presents a problem if the initial count is odd, as we need to reach 0 to trigger the terminal count condition.

Odd Count Logic

Within the counter is a flip-flop I will call the 1/3 flip-flop. This flip-flop is initially 0.

• If the CE is odd, the 8253 will decrement it as follows:
  • If the 1/3 flip-flop is 0, the CE will be decremented by 1. This sets the CE to an even value.
  • If the 1/3 flip-flop is 1, the CE will be decremented by 3. This sets the CE to an even value.
• If the CE is even, the 8253 will decrement it by 2.
• When the counter reaches terminal count (0), CE is reloaded by CR, and the 1/3 flip-flop is toggled.

This is a somewhat awkward way of accounting for the one missed clock period per cycle we would otherwise accumulate over time with an odd count. The result of this logic is that the resulting square wave is HIGH for \(\frac{N+1}{2}\) clocks and LOW for \(\frac{N-1}{2}\) clocks.

Note: The 8254 implements the logic for Mode 3 differently than the 8253. Refer to the 8254 datasheet for an accurate description if you are emulating an 8254.

The counter also has an output flip-flop that it uses in this mode to toggle the state of the OUT pin when terminal count is reached.

Output Behavior

• After mode set: OUT → HIGH
• At terminal count: OUT toggles state

GATE Behavior

• Edge-triggered
• GATE HIGH: Trigger. The CR is loaded into the CE on the next clock edge. Counting enabled.
• GATE LOW: OUT → HIGH. Counting disabled.

Reload Behavior

• Writing a new count during an active count will not affect the current count until either a terminal count or a GATE trigger.
• CR is automatically loaded into the CE after terminal count is reached, restarting the count.

Timing

Figure 6: Timer Mode 3 - Square Wave Generator Timing

Mode 4 — Software Triggered Strobe

Summary

When the initial count reaches 0, OUT produces a one-clock-wide low pulse. This is similar to Mode 2, but with a distinct difference - in Mode 2, OUT goes low on a count of 1, and HIGH again on a count of 0. In Mode 4, OUT goes low on a count of 0, then HIGH again on the next clock edge. The counter will continue to count, rolling over from 0 to 0xFFFF, but will not affect the state of the OUT pin until the next count value is written.

Counting begins when the initial count is written (the “software trigger”).

Output Behavior

• After mode set: OUT → HIGH
• At terminal count: OUT → LOW for one clock period

Count Loading

• After writing the count, the CR is loaded into the CE on the next clock edge. Counting begins automatically on the following clock edge.
• Writing a new count during an active count will trigger a CR to be loaded into the CE at the next clock edge.
  • In LSBMSB mode, writing the first byte only has no effect.

GATE Behavior

• Level-triggered
• GATE HIGH: Counting enabled.
• GATE LOW: Counting disabled.
• GATE does not affect OUT.
• GATE does not trigger a reload of the counter.

Timing

Figure 7: Timer Mode 4 - Software Triggered Strobe Timing

Mode 5 — Hardware Triggered Strobe

Summary

Similar to Mode 4, but triggered by a LOW → HIGH transition of GATE. In Mode 5, OUT goes low on a count of 0, then HIGH again on the next clock edge. The counter will continue to count, rolling over from 0 to 0xFFFF, but will not affect the state of the OUT pin until the counter is retriggered by the GATE pin.

Note: The count starts running as soon as Mode 5 is selected - but you’ll note that the CE is not loaded until a GATE trigger. Presumably, the counting element still contains whatever it had in it when the mode was set, but this has not been verified.

Output Behavior

• After mode set: OUT → HIGH
• At terminal count: OUT → LOW for one clock period

GATE Behavior

• Edge-triggered
• GATE LOW -> HIGH: Trigger. The CR is loaded into the CE on the next clock edge. Counting enabled.
• GATE does not affect OUT,

Reload Behavior

• Writing a new count value during an active count will not affect the current count until either a terminal count or a GATE trigger.

Timing

Figure 7: Timer Mode 5 - Hardware Triggered Strobe Timing

Mode Summary Table

Edge Cases

Some interesting edge cases have been observed. Consider the following scenario:

• A timer channel is set to Mode 2 - Rate Generator, RW mode LSBMSB, and an initial count written, starting the count.
• Only the LSB of a new count is written.
• The timer reaches terminal count. What value is loaded into the Counting Element?
• Once the Counting Element has been reloaded, what happens when the MSB of the new count is then written?

If you have studied the counter channel block diagram, you may be able to figure out what should happen. The \(\text{CR}_m\) and \(\text{CR}_l\) registers are used to hold the programmed initial count, and the CE is reloaded from these registers. In addition, the counter keeps a flip-flop to keep track of the progress of writing a new count, and will write the contents of the CR registers to the CE when the write is complete (depending on mode).

The Intel 8254

The 8254 is an improved model of the 8253 and was used in the IBM AT. It would become the standard timer chip in PC compatible systems for many years.

Changes in the 8254

• Faster clock inputs
• A channel state read-back command
• Resolves the issue with the 8253 where reads and writes to the same channel could not be interleaved without leaving the chip in an undefined state.
• Modified the logic of Mode 3 - Square Wave Generator.

If you wish to emulate the 8254 instead of the 8253, there’s no real problem with doing so.

Emulation Tips

Implementation Priority

• Implement these modes first:
  • Mode 3, Square Wave Generator
  • Mode 2, Rate Generator
  • Mode 0, Interrupt on Terminal Count
• Connect the output of Timer Channel 0 to IRQ0
• Connect the 8255 PPI Port B bit 0 to the GATE of Timer Channel 2

Primary Emulation Resources

• (alldatasheet.com) 8253 Datasheet
• (alldatasheet.com) 8254 Datasheet
• (wiki.osdev.org): Programmable Interval Timer - Mostly describes the 8254

Further Reading

• (wikipedia.org): Intel 8253
• (intel.com @ archive.org): 8254/82C54 Programmable Interval Timer

References

Programmable Peripheral Interface (8255 PPI)

The Intel 8255 PPI is a general-purpose IO chip that provides 24 configurable, bidirectional I/O pins.

The 8255 was used in a number of systems, and even a few mouse controller cards.

The IBM 5150 and 5160 utilize the PPI to receive scancodes from the keyboard interface, read the system’s DIP switches, read motherboard status lines and write control signals.

The PPI is a moderately complex chip with several modes of operation. Perhaps unique to all the support chips you need to emulate, the vast majority of the PPI’s extended capabilities and modes can be completely ignored by a basic PC emulator.

Intel 8237 DMA Controller

The Intel 8237 DMA (Direct Memory Access) Controller enables efficient data transfers between memory and I/O devices without CPU intervention. In the IBM PC, it coordinates data transfer to and from floppy and hard drives, as well as performing DRAM refresh cycles.

Overview

The 8237 provides four independent DMA channels, each capable of transferring data between memory and peripherals. In theory, the 8237 is capable of performing memory-to-memory transfers as well, but its implementation in the IBM PC prevents it from doing so.

IBM PC DMA Configuration

Note: Not all hard disk controllers use DMA. Notably, most models of the XTIDE do not.

Hardware Interface

I/O Ports (8237A-5)

Page Registers

The DMA page registers are not part of the 8237 itself, but are implemented on the motherboard. They are provided here for convenience.

Note: The page register addresses are mapped out of order from their respective channels. Take note of the assignments.

• 0x81: Channel 2 Page Register (Address bits 16-19)
• 0x82: Channel 3 Page Register (Address bits 16-19)
• 0x83: Channel 1 Page Register (Address bits 16-19)

The IBM AT added a page register for Channel 0, but this is not implemented on the PC/XT:

• 0x87: Channel 0 Page (bits 16-19)

DIP switches

DIP Switch #2 on the IBM 5150

Dual In-line Package (DIP) switches are small electrical components designed to enable a user to configure the operation of a device. DIP switches have an indicated ON position printed on the switch package. In this manner some switches can be turned ON and others turned OFF. DIP switches are not often marked with their effects - typically you would need to consult a manual to determine how they should be set.

Although convenient for device designers to implement, they are somewhat inconvenient for users in that they require a small tool to physically set. On the PC, accessing the DIP switches requires removing the case cover and navigating through any cabling and expansion cards that may be in the way.

The IBM 5150 has two configuration DIP switches. The first one, SW1, is concerned with configuring the amount of memory installed in the system. The second set of DIP switches, SW2, is used to indicate what hardware is installed in the system.

The IBM 5160 XT BIOS added auto-discovery of the amount of memory installed in the system, and so SW1 was removed. The operation of SW2 on the XT is otherwise similar.

Some expansion cards have DIP switches, which are sometimes accessible from the outside of the case through a cut-out in the IO bracket. The IBM EGA card is one such example.

Reading DIP Switches

One gotcha when reading the DIP switches on the PC is that they will read logically inverted from what you may intuit from their physical state. If a DIP switch is set to ON, it will read as a logical 0. If a switch is set to OFF, it will read as a logical 1.

A small schematic will help explain why:

When a switch is OFF, it is electrically open. Pull-up resistors connected to the output side of the switches make them read as logically 1. When a switch is ON, it is electrically closed. The other ends of the switches are connected to ground, and so current flows through the switch and the output side of the switch reads as logically 0.

This was a common way to implement a DIP switch as a connection to ground is a lot easier to find on a PCB than a connection to VCC.

The IBM PC/XT Keyboard Interface

The XT keyboard interface, as it will be referred to from now on, is one of the most frequently misunderstood systems on the IBM PC, confusing both emulator authors and retro-programmers alike. It is easy to write a program that uses the keyboard in a way that works fine on an AT (or in DosBox), but fails on a more accurate XT emulator or real XT system. This is due to some peculiarities of the XT interface, which will be explained here.

The Host Keyboard Interface

The low-level, host-facing interface to the keyboard is implemented via the 8255 PPI. The keyboard is controlled via two bits on Port B, 61h, and the scancodes themselves are read out of Port A, 60h. These particular ports became somewhat standard, and so are often implemented on systems which do not even have an 8255 at all.

The Hardware Keyboard Interface

PB6 is typically used to reset the keyboard. It is wired up to a driver that will connect the keyboard clock line to ground. The control pin of the driver is active-low, which is why setting PB6 to 0 will perform this function, and setting PB6 to 1 allows the keyboard to operate normally.

Here is a simplified schematic:

See the Model F section for more specific details, but if the keyboard clock line is held low for 20ms the keyboard will perform a reset/self-test. The BIOS sometimes does this, but applications usually do not.

The keyboard interface is a typical two-wire serial connection with a clock and a data line. Both of these are pulled high, with either the PC or the keyboard able to drive the lines low. The PC drives the lines low with dedicated drivers; the keyboard takes advantage of the open-collector outputs of its 8048 microcontroller.

This scheme allows simple hardware flow control - when the PC has the clock or data line pulled low, the keyboard cannot send data. The keyboard’s microcontroller can detect when the PC has either line held low, and knows to wait as the PC must either be busy, or requesting a reset. Keys pressed while the data line is held low by the PC will be stored in the keyboard’s internal FIFO until they can be sent. If this FIFO is full, then any additional keystrokes will be lost.

Each scancode is sent as a series of 9 bits. A rising edge of the keyboard clock line triggers the PC to sample the data line, shifting the resulting bit into a 74LS322 shift register, U24. The first bit, called a start bit, is always 1. This is used to good effect - when the Qh output of U24 goes high, this triggers various circuitry that clamps down on the keyboard data line, pulling it low after an additional clock. At this point, the shift register contains the entire 8-bit scancode, which can then be read out of PPI Port A.

Bits are sent over the wire from least-significant (bit 0 of scancode) to most-significant. Here is a logic analyzer capture of the ‘G’ key being pressed (scancode 0x22):

Keyboard scancode 0x22 timing trace (Click to zoom)

Here is a simplified schematic:

Note that a complete scancode being received directly triggers IRQ1, and only writing 1 to PB7 will lower IRQ1 again.

Setting PB7 to 1 does several things:

• It clears the contents of the keyboard shift register U24, making its Qh output low for at least the next 8 clocks.
• It disables the parallel outputs of the keyboard shift register U24, making it impossible to read a scancode.
• It resets the flip-flop controlling IRQ1 and the keyboard data line. This forces IRQ1 low, and allows the keyboard to drive the data line.

Therefore, to read the keyboard, software must set PB7 to 1 and then reset it back to 0 after each scancode is read.

Floppy Disk Concepts

If you are already familiar with floppy disks, their operation and organization, skip ahead to the floppy data encoding section.

The floppy disk was the most common form of removable, rewritable storage on the IBM PC. Even when physical distribution of commercial software had moved to the CD-ROM, users still found the floppy disk useful day-to-day for moving files between systems. The main advantage of the floppy disk was its sheer ubiquity — nearly every PC had a floppy drive.

The floppy disk gets its name from its flexibility. If held only by one corner, the disk would easily flex or ‘flop’ when moved.

The floppy disk was originally invented by IBM, which coined the term diskette to refer to their 8“ floppy disks, sometime around the time the IBM 3740 was introduced; however, floppy disks had already been in use for several years by then. The name diskette was frequently seen on floppy disk retail packaging, but colloquially, most people just called them floppies.

A floppy drive was technically an optional add-on for the original PC, but the near total absence of software titles available for the PC on cassette made at least one floppy drive a mandatory purchase.

Floppy disks have existed in numerous forms over the entire history of computing, but the original format used on the PC was the 5.25“ diskette.

Basic Floppy Operation

A floppy disk is a ferromagnetic medium upon which data can be stored by magnetizing the medium in specific patterns. Data is read from and written to the disk via magnetic heads located within a floppy disk drive. A floppy disk drive stores data on a floppy disk in a series of concentric rings called tracks. The magnetic heads travel on a linear carriage controlled by a stepper motor which positions the heads above a specific track to be read or written.

The 5.25“ Diskette

A 5.25“ floppy disk consists of a vinyl jacket covering a circular disc of biaxially oriented polyethylene terephthalate, more commonly known by its brand name, Mylar. A polymeric coating containing carefully milled ferric oxide powder was applied to the surface of this disc, which could then be deliberately magnetized to store specially-encoded data. This inner disc is sometimes referred to as the cookie (or biscuit, if you are from the UK).

The vinyl jacket of a floppy disk has several cutouts. A central hole exposes the inner rim of the Mylar disc which is clamped against the floppy drive spindle when a disk is inserted into a drive and the drive door (sometimes just a lever) is closed. The drive’s spindle motor could then rotate the cookie within the stationary jacket, typically around 300RPM.

A pill-shaped cutout called the data window exposes the usable region of the cookie on both sides, accommodating the full linear travel of the drives’ magnetic heads.

A 5.25" Floppy Disk (Click to zoom)

Near the central spindle, a circular cutout in the jacket allows a photosensor to detect light through a small hole in the Mylar disc called the index hole. When this photosensor — called the index sensor — detects light through the index hole, the drive generates an index pulse. The floppy controller uses the index pulse to know where to start initializing or formatting a track of data. Once a track has been fully written, the index sensor only serves as a useful operational timeout — any disk operation typically must complete within two revolutions of the disk or two index pulses. Not all computer systems utilized an index sensor, with the Apple II the most famous of systems that did not.

The write-protect notch is a rectangular cutout on the right side of the floppy disk that permits data to be written to the floppy disk. A small sticker could be folded over the side of the floppy disk to cover this notch, which would then prevent the host computer from writing data to the disk.

Note

The effect of a write-protect sticker is reversed on 5.25“ disks from the logic used by earlier 8“ disks — on an 8“ disk, you apply a sticker to make the disk writable! This change may have been driven by the increasing importance of commercial software distribution on floppy, allowing manufacturers to produce “notchless” disks that couldn’t be easily overwritten.

The inside of the jacket contains a dust-collecting liner which served the essential function of keeping the inner cookie clean. This part of the floppy may be considered consumable; over time only so much dust can be captured and larger, grittier particles trapped in the liner may even cause damage. Therefore, storing floppy disks in closed, dust-free containers was well-advised.

5.25“ floppy disks were somewhat fragile. They were susceptible to damage from improper handling such as creasing or bending, or directly touching the magnetic coating visible through the data window. Exposure to magnets could damage or erase the data stored on the floppy. That said, if treated with care, the floppy disk was a fairly reliable storage medium.

Over time, floppy disks have faced new challenges. Heat and humidity in long-term storage can lead to the oxide coating flaking off, or mold growth on the cookie which can contaminate the inner lining. Even so, if stored carefully, many floppy disks can still be read a half-century later.

The original floppy diskette was 8“. When the 5.25“ disk was introduced, its smaller size required it to be distinguished from the standard 8“ floppy, and so 5.25“ diskettes were sometimes called minifloppies. Seeing the term minifloppy is a good sign you are reading an older reference.

Single and Double Sided Floppies

The oldest floppy drives were single-sided — they possessed a single magnetic head to read and write data, which was done from the bottom side of the floppy if inserting it label-side up. Single-sided disks could sometimes be flipped over to use the other side, much as you might flip over a vinyl record. These so-called flippy disks could be easily identified by the presence of two index hole cutouts — and sometimes two write-protect notches.

A double-sided floppy drive has two magnetic heads, which clamp together to press against opposite sides of the cookie. You can see an image of a double-sided drive’s magnetic heads below. Head 0, which accesses side 0, is located on the bottom, with side 1 accessed from the top.

The top head is usually on some sort of actuator, where it can be lowered onto the disk surface to clamp the cookie between both heads. This clamping action is called head loading. In a single-sided drive, a foam pad typically provides the clamping force in the absence of an opposing head.

A double-sided floppy drive's magnetic heads

5.25“ Floppy Capacities

5.25“ floppy disks on the IBM PC were available in the following capacities:

High Density 5.25“ Drive Quirks

One way high-density 5.25“ disk drives increased capacity was by doubling the number of tracks written to high-density 5.25“ diskettes. To do so, the size of the magnetic head itself was made thinner. This can create issues when writing data to double-density diskettes that are then read in a double-density drive with a wider head.

Many high-density 5.25“ drives increase the rotational rate of the cookie to 360RPM, although this can often be controlled by a jumper on the drive. Leaving this setting at 360RPM can cause inaccurate flux timing readings when making flux-level images of double-density diskettes. This can be corrected after the fact, but is not ideal as it can interfere with proper imaging of some copy protection techniques. It is best to image double-density floppy disks in a double-density drive, or at least a high-density drive with the 300RPM mode selected.

The 3.5“ Diskette

The 3.5“ floppy disk was an improvement over the 5.25“ floppy in capacity, durability, and convenience. The 3.5“ floppy disk employed a rigid plastic shell and a metal, spring-loaded shutter to protect the cookie from dust and contact with fingers. A rectangular hole — which could be covered by an integrated plastic slider — controlled whether the disk could be written to or not, meaning awkward stickers were no longer required. When the hole was unobstructed by the slider, the disk was write-protected.

A 3.5" Floppy Disk (Click to zoom)

Later high-density variations of the 3.5“ floppy could be identified by a second hole on the opposite side from the write-protect hole. This allowed the drive to recognize the disk as high density. In addition, a “HD” logo was usually printed on or molded into the plastic shell.

3.5“ diskettes are sometimes referred to as microfloppies.

Note

In more recent years, a contentious debate can occasionally arise over whether the hard-shelled 3.5“ disks were referred to as “floppy disks” — primarily due to their distinct lack of being floppy. The term “floppy disk” generally applied to 3.5“ disks as well in English-speaking countries with the exception of South Africa, where 3.5“ disks were routinely called “stiffy disks”¹.

In other countries, other terminology may have been common, but most computer users would have been familiar with the term “floppy disk” in reference to 3.5“ diskettes due to the predominance of US and UK-based media.

3.5“ Floppy Capacities

3.5“ floppy disks on the IBM PC were available in the following capacities:

Magnetic Encoding

A floppy disk, like any digital medium, ultimately stores 0s and 1s. A floppy disk encodes binary bits by means of changing magnetic flux.

The Mylar cookie of a floppy disk has a polymeric coating applied to it containing very fine, ferromagnetic particles. On a blank, unformatted disk, these particles are not magnetized in any specific direction. To write data to a floppy disk, the drive magnetizes these particles in specific patterns along concentric rings called tracks.

It might help to visualize the ferromagnetic coating as if it were a number of very small bar magnets with a north and south pole. Data is encoded by alternating the magnetic polarization along a single track as the disk rotates beneath the write head. This is called longitudinal recording.

Note

Later 2880KiB — or “Extra-high density” — floppy drives utilized perpendicular recording, which will not be discussed here.

The ferromagnetic coating is magnetized by the drive’s magnetic write head. A photograph of such a head can be seen below.

The floppy disk write head in a TEAC FD-55BR disk drive

A floppy disk write head

By periodically changing the magnetic orientation, small regions where the polarity flips are also created — these regions are called flux reversals or flux transitions.

A flux transition (representational, not to scale — click to zoom)

When reading a floppy disk, it is these transitions that the drive detects, via Faraday’s Law of Induction. The change in the magnetic field induces a voltage in the coil attached to the read head, creating an electrical signal that can be amplified and turned into a read pulse. These read pulses are sent to a floppy controller, which uses the time between each pulse to recreate the actual bits encoded on the disk.

Data Encoding

The actual bits stored on a floppy disk represent an encoded form of the data written to the disk. Earlier 8“ floppy disks typically used frequency modulation (FM) encoding, whereas most floppy disks for the PC utilize modified frequency modulation (MFM) encoding.

Although FM mode was seldom used, the IBM PC floppy controller could be operated in both FM and MFM modes. The controller would need to be set to the correct mode to successfully read back data originally written with that mode.

The purpose of both encoding schemes is to add clock bits that provide timing information, a technique known as clock recovery.

A requirement for successful clock recovery from the encoded bit stream is ensuring that 1 bits are regularly encoded. This in turn ensures that regular flux transitions are written to the disk. The absence of a flux transition over too long a period risks creating an unstable condition where data cannot be reliably read. As a general rule, no more than three consecutive 0 bits are allowed in the encoded bitstream written to a floppy disk track.

The next chapter, Floppy Data Encoding, covers this subject in more detail.

Density

Density in terms of floppy disks refers to how tightly and efficiently data can be encoded onto a track. Initially this was a combination of both encoding methods and packing flux transitions more tightly together.

All standard floppy disk formats used on an IBM PC use MFM encoding. As this was a space savings improvement over the original FM encoding, this led to the terminology of the double-density diskette often seen on retail packaging and diskette labels. If you were ever curious if there was a “single-density” diskette — these were actually referred to as standard density, but were never used on the PC.

PC floppy disk encoding never moved beyond MFM. Therefore, when high-density and extra-high-density disks emerged, this extra density was simply the result of packing flux transitions more tightly together. This usually necessitated more advanced formulations of ferromagnetic coatings, using more exotic or specially-doped oxides.

Rotation

If viewed from the top, a floppy disk drive rotates the cookie in a clockwise direction, and therefore data is written to the cookie counter-clockwise. When viewed from beneath the drive (from the perspective of head 0), the cookie rotates in a counter-clockwise direction, and therefore data is written clockwise. This rotation is often reflected by disk visualization software.

Most floppy drives on the PC rotate the cookie at 300RPM except for 5.25“ high-density disk drives, which often rotate the cookie at 360RPM.

Note

Some 3.5“ drives — mostly used on non-IBM-PC compatible systems — could rotate at 360RPM, or even at variable RPM depending on which track was being read. These will not be discussed further in this book.

Floppy Disk Organization and Addressing

A floppy disk stores concentric rings of data called tracks. Tracks are identified by a 0-based index, starting at the outer extent of the drive head’s travel (closest to the edge of the disk), counting upwards as the tracks proceed inwards toward the spindle hole. This index is called the cylinder number. A track can be uniquely identified by combining the cylinder number with a specific head, indicating which side of the floppy the track is on.

Tip

The distinction between tracks and cylinders may be somewhat confusing. Think of it as a coordinate system where a track is a combination of cylinder and head — the cylinder specifies how far from the outer edge of the data the drive head should be positioned, and the head determines on which side of the disk the track is located. On a double-sided disk, a cylinder can therefore refer to two unique tracks, one on each side of the disk. On a single-sided disk, the concepts of track and cylinder are fundamentally equivalent.

A floppy drive selects a specific cylinder to operate on by physically moving the magnetic heads until they are over the cylinder. Since the carriage the magnetic heads are on is actuated by a stepper motor, the process of moving from one cylinder to the next is called stepping.

Most PC floppy drives contain a special sensor that can indicate when the magnetic head is positioned at the outermost cylinder. This is called the track 0 sensor. If the position of the magnetic head ever becomes indeterminate, the drive can be recalibrated by seeking to track 0.

Each track contains one or more sectors. Each sector is identified by a sector ID consisting of the cylinder number, head number, sector number, and a sector size specifier. Sector numbers typically begin with 1 on each track by convention, but nothing actually guarantees this.

The combination of cylinder, head, and sector number can uniquely identify a sector on a normally formatted floppy disk. This is sometimes referred to as CHS addressing, which you may also see referenced in the context of early hard drives.

Sectors are aligned on each track by synchronizing to the index pulse created by a photodiode that detects light shining through the physical index hole. With each sector on each track aligned, a floppy disk resembles something like pie slices. Individual sectors are separated by small areas of padding called sector gaps.

Floppy disks are often visualized using diagrams with an exaggerated inner diameter with the index position at the right side, like the one below.

A typical sector layout on a 5.25" 360KiB floppy disk, as seen from head 0 (not to scale)

If one could see the actual track layout on a 5.25“ disk, it would be condensed into the region visible through the data window and accessible along the full travel of the floppy drive’s head carriage. The following diagram attempts to reproduce such an image:

A typical sector layout on a 5.25" 360KiB floppy disk, as seen from head 1

The specification of how data is organized on any given track of a floppy disk is called its track format.

The track format of IBM floppy disks is sometimes referred to as System 34 format, in reference to the IBM System/34, which utilized this format before the PC.

The process of writing out a standard format consisting of a prescribed number of sectors is called formatting. This operation can be performed by a floppy controller with a special formatting command on a per-track basis, but most users will be familiar with formatting an entire disk at a time using a utility such as MS-DOS’s FORMAT.COM.

Sectors: Soft vs Hard

All floppy disks for the PC are soft-sectored. You may see this description as you read various references and wonder what it means. Some earlier 8“ floppy disks were hard-sectored in that they had physical holes punched into the cookie that delineated sector boundaries on the disk. These holes were placed on a radial path aligned with the index hole and so could be read via the same photosensor.

Sectors may be placed anywhere on a PC-formatted floppy disk, thus we can say they are the opposite of hard-sectored: soft-sectored.

Standard PC Floppy Disk Specifications

1. Internet Archive full-text search for “stiffy disk” ↩

Floppy Data Encoding

If you are not already familiar with floppy disks, their operation and organization, you may wish to review the prior section on floppy disk concepts.

Before data can be written to a floppy disk, it must first be encoded using a scheme to make the data compatible with storage via timed flux transitions.

An encoding scheme has the primary job of making clock recovery possible, since data transfer to and from a floppy drive is a serial stream with no independent clock line. By inserting clock bits, an encoding scheme can allow the controller to synchronize with the rate data is being streamed from any given floppy drive while accounting for factors such as slightly too fast or slightly too slow spindle motors, RPM wobble, or basic signal jitter.

A variety of encoding schemes have been used on floppy disks over the years, but only one — MFM — is primarily relevant on PC.

Almost all floppy disks written for the IBM PC use primarily MFM encoding for user-accessible data.

Note

FM-encoded sectors do regularly appear on commercially duplicated software titles, usually on the very last track of a floppy. These are called duplication marks. They often contain metadata about the publisher, duplication parameters, and sometimes even the copy-protection scheme employed. It is not critical that your emulator be able to read them, and only certain disk images can encode them, anyway.

FM Encoding

FM encoding is conceptually very simple. 1 bits are inserted between each data bit of the data stream to be encoded. An FM-encoded data stream will begin with an initial 1 clock bit.

If we begin with the bit sequence 1100_0101, after inserting clock bits, we are left with the sequence 1111_1010_1011_1011.

The clock and data bits interleave like so:

A trivial encoding table can be constructed:

Since there are only two possible output sequences, FM-encoded data is magnetically encoded with two discrete flux transition periods, which we will call short and long transitions. These periods refer to the time between a pair of flux transitions.

Note that FM encoded data becomes twice as long as the source data it encodes. For this reason other, more efficient encoding schemes became more popular.

MFM Encoding

MFM encoding improves on FM by only inserting clock bits where they are needed for clock recovery. A clock bit is written before a 0 data bit only when the previous data bit was also 0; all other clock positions are left empty, represented as 0 in the encoded cell stream. Since encoding any particular bit sequence into MFM requires knowledge of the previous bit in the stream, we can say that MFM is a stateful encoding scheme.

The mathematical representation of MFM encoding can be written as:

$$ (x, y, z) \to (x, \overline{x \vee y}, y, \overline{y \vee z}, z, \ldots) $$

Some sort of data leader or sync region may be needed to initialize a MFM data stream since there will always be a first bit in any stream, which will by definition not have a valid previous bit.

If we begin with the same bit sequence as before, 1100_0101, and assume that the previous data bit was 0, MFM encoding gives us the sequence 0101_0010_1001_0001.

The clock and data cells interleave like so:

When encoding a stream of bits into MFM one has to account for the previous data bit. In the table below, - means that no clock bit is inserted:

Although MFM still doubles the length of the encoded bitstream, it allows for more efficient representation as time between flux transitions, reducing the total number of transitions required. MFM is twice as efficient as FM as a result.

MFM-encoded data is magnetically encoded with three discrete flux transition periods. These periods refer to the time between a pair of flux transitions.

Note

You may see references begin the bitwise expansion of a flux transition time with either a 0 or 1, putting the 1 bit on either end. Either notation is functionally equivalent, since the period between flux transitions essentially defines the number of 0’s between two 1’s.

Marker Sequences

FM and MFM encoding specify standard rules by which data is encoded into clock and data bits, and subsequently into flux transitions. Breaking those rules would naturally produce an illegal stream, which we might refer to as an MFM error in the case of MFM encoding.

There are however circumstances where an invalid MFM sequence can be allowed. One such use case is for defining track markers. A track marker is a specially encoded run of data that uses a unique, detectable pattern of clock bits that essentially allows it to stand out from normally-encoded data. A sort of out-of-band signal, if you will.

For example, an MFM sector ID address marker (IDAM) contains three specially-encoded A1 bytes. Each has the data pattern A1, but uses a clock pattern of 0A instead of the normal MFM clock pattern of 0E. This creates a single, missing 1 bit in the clock signal - enough for a floppy drive controller to identify the sequence as a marker.

Primary References

• (floppy.cafe) MFM Encoding

Floppy Drive Controller

IBM PC/XT systems outfitted with a floppy drive had an “IBM 5.25” Diskette Drive Adapter“ card installed in one of the available expansion slots.

For a good look at the Diskette Drive Adapter, see minuszerodegrees.net.

At a Glance

Controller Overview

The IBM floppy drive controller, as we’ll refer to it here, was a collection of 74-series logic chips and a 16.0Mhz clock crystal supporting the “brain” of the card, a NEC µPD765A (NEC 765) floppy drive controller chip (or the more-or-less identical Intel P8272A).

Note

Die photography of the P8272A has revealed the numbers ‘765’ directly on the die - implying Intel licensed NEC’s design.

The IBM floppy controller could support up to four floppy disk drives, although configurations of more than two were uncommon. Drives 0-3 would be assigned the drive letters A-D up until MS-DOS 5.0, whereupon DOS started to reserve drive letter C for hard disks. It might feel a bit cursed to have a floppy disk as drive C, but if you did indeed have three drives connected and an earlier version of MS-DOS, that’s what you’d end up with.

The NEC 765 takes an 8MHz clock, divided once from the card’s 16Mhz crystal.

The 765 doesn’t perform every function needed by a floppy controller. Notably, the controller’s voltage-controlled oscillator (VCO), a crucial part of the controller’s phase-locked-loop (PLL) is external to the 765, although the 765 has pins for interacting with it. Also external to the 765 is the data separator circuitry.

Operation

On the IBM PC/XT, the floppy drive controller is operated by the BIOS in DMA mode exclusively. It is possible to operate the controller in polled-io mode (PIO) in a manual fashion, but there are severe disadvantages to doing so - as was seen on the IBM PCjr which lacked a DMA controller. The lack of DMA prevented such operations as transferring data via the serial ports and floppy disk drive at the same time.

The 765 operates as a state machine with three basic operational phases:

• During the command phase the controller receives bytes from the host that instruct it to perform a specific operation.
• During the execution phase the controller carries out the operation specified in the command phase.
• During the result phase the controller provides status information to the host describing the result of the execution phase.

The 765 is capable of running some operations, such as seek and recalibrate, on multiple drives simultaneously.

I/O Ports

The IBM Diskette Drive Adapter decodes the following IO port addresses:

The Digital Output Register

The IBM controller card adds a main control register external to the 765, called the Digital Output Register or DOR. The DOR has several functions - it selects a specific drive as the target of operations, it can reset the 765, it can enable or disable interrupts and DMA, and it can turn on and off the attached floppy drive motors.

The DOR is a write-only register implemented with an 74LS273 8-bit register chip.

Drive Selection Bits

The two least significant bits (Bits 0-1) of the DOR control which floppy drive is selected.

Important

If a drive’s motor is not on, selecting it in the DOR will do nothing until the motor is turned on.

Note

To avoid confusion, be aware that the DOR is the only drive selection method used by the IBM floppy drive controller. The NEC 765 command set includes fields that select which drive the operation is intended to target. Under IBM’s controller design, these bits do nothing externally - the 765 is not in control of which drive is selected. You can verify this yourself by noting the 765’s unit select pins, 28 and 29, are not connected on the schematic.

Reset Bit

The DOR’s \(\overline{\mathrm{RESET}}\) bit 2 drives the 765’s active-high RST pin (1) via an inverter. When a 1 is written to bit 2, the 765’s RST pin is pulled low, holding the controller in reset.

Note

The IBM floppy controller card ties the 765’s RDY pin (35) high. This causes the 765 to generate an interrupt after coming out of the RESET state after “1-25ms”, according to the datasheet. The controller is reset quite often during normal operation.

The 765 Registers

The 765 contains five status registers in total. The first of these is the main status register (MSR). The MSR is the only status register that may be read at any time. The contents of the other status registers, ST0—ST3, are sent to host during the controller result phase.

The Main Status Register

The BUSY bit

The BUSY bit is set when the controller is executing a command, and is only cleared when the last byte of the result phase has been read by the host CPU. It can be used as a general indication that a new command should not be sent to the CPU.

The DIO bit

The DIO bit controls the direction of transfer to or from the controller. The CPU should only send data to the controller when DIO is 0. When DIO is 1, the controller is not ready to receive data — it expects to have data to send to the CPU.

The MRQ bit

The MRQ bit can be usefully combined with the DIO bit to control data transfer to and from the controller.

Note

This bit may also be labelled as RQM in technical references.

Status Register 0 (ST0)

Status Register 1 (ST1)

The No-Data Bit

The No-Data bit is set under the following conditions:

• The FDC could not find the requested sector during execution of READ DATA, WRITE DELETED DATA or SCAN
• The FDC could not read the ID field during execution of READ ID
• The FDC could not find the starting sector during execution of READ CYLINDER.

Status Register 2 (ST2)

Status Register 3 (ST3)

Important

Remember that on the IBM floppy controller, the 765’s unit select pins are not connected and do not drive selection of floppy drives.

Controller Commands

The 765 supports 15 different commands:

Commands consist of 2—9 command bytes, sent during the command phase. The command will then enter the execution phase. When complete (or on error) the command enters the result phase and various status register bytes will be made available to read out from the data register.

The first command code byte 0 is common to all commands and contains the command code as given in the table above, along with operational flags. These flags are not always applicable to each command. The flags applicable to each command are noted in the table above.

Command Code Byte 0

Command Code Byte 1

The Read Data Command

The Read Data command is opcode 06h.

The Read Data command searches for the sector ID matching the specified cylinder, head, sector and sector size. The matching sector must have a normal data address mark (DAM).

In DMA mode, it will read successive sectors that have a normal DAM until terminal count. In PIO mode, it will read successive sectors that have a normal DAM until EOT is reached.

If the MT flag is set, once the last sector of side 0 is transferred, the FDC proceeds to repeat the operation on side 1.

The Read Data command behaves as follows depending on the value of the SK flag:

After the data is transferred, the command enters the result phase.

Status Flags Affected

Command Format

The Read Deleted Data Command

The Read Deleted Data command is opcode 0Ch.

The Read Deleted Data command searches for the sector ID matching the specified cylinder, head, sector and sector size. The matching sector must have a normal deleted data address mark (DDAM).

In DMA mode, it will read successive sectors that have a DDAM until terminal count. In PIO mode, it will read successive sectors that have a DDAM until EOT is reached.

If the MT flag is set, once the last sector of side 0 is transferred, the FDC proceeds to repeat the operation on side 1.

The Read Deleted Data command behaves as follows depending on the value of the SK flag:

After the data is transferred, the command enters the result phase.

Status Flags Affected

Command Format

The Read ID Command

The Read ID command is opcode 0Ah.

The FDC returns the fields of the next Sector ID encountered on the track.

The MT and SK flags are not valid for this command and should be 0.

Status Flags Affected

Command Format

The Read Track Command

The Read Track command is opcode 02h.

Unlike what its name might suggest, Read Track does not actually read a raw track. Instead, it reads all sectors on a track, regardless of ID or CRC validation.

The Read Track command first waits for the index signal. It then returns the data for each sector encountered, in order. The Sector ID of the first sector is checked against the values given to the command for the purposes of setting the ND bit in ST1, but a mismatch is not an error and does not stop command execution.

The MT and SK flags are not valid for this command and should be 0.

Status Flags Affected

Command Format

The Scan Commands

The three scan commands, Scan Equal, Scan High or Equal, and Scan Low or Equal, behave identically other than the mathematical expression they evaluate for each pair of bytes processed.

In each of the three commands, the FDC performs a comparison (the scan condition) between bytes read from the disk and bytes provided by the host. If this comparison is true for the entire sector, the scan condition is said to have been satisfied or tha a scan hit has occurred, at which point the scan operation will enter the result phase.

The value of FFh is special, and is treated as a wildcard. If either the byte from the disk or the byte from the host is FFh then the comparison will be considered true. This allows use of FFh by the host to mask the comparison bytes provided to the FDC.

If a sector does not satisfy the scan condition, the FDC will continue with the next sector to scan based on the STP step parameter. If STP == 1, this will be the next consecutive sector number. If STP == 2, then the FDC will skip the next consecutive sector number.

Important

Regardless of the STP parameter, the FDC must be read the last sector on the track as specified by EOT. Unexpectedly encountering the index pulse during the scan operation will result in abnormal termination.

If EOT is reached or terminal count occurs before a scan hit occurs, then the scan operation ends with a scan not satisfied condition. In the case of a terminal count, the operation ends after the current byte being compared.

Scan Command Operations

Status Flags Affected

Command Format

The Specify Command

The Specify command sets three timing variables for the drive as well as setting the FDC operational mode to DMA or PIO modes.

The Specify command has no result phase.

Command Format

Command Byte 1: Specify Timing 0

Command Byte 2: Specify Timing 1

Invalid Commands

Any unrecognized or unsupported command code will return a single ST0 byte with a IC of 10b, or abnormal termination. The value of the ST0 byte in hexadecimal will be 80h.

Datasheet

• (archive.org) μPD765A Single/Double Density Floppy Disk Controller

Primary References

• (archive.org) IBM 5-1/4“ Diskette Drive Adapter

• (debs.future.easyspace.com @ web.archive.org) Programming Floppy Disk Controllers

Display Concepts

This section describes general display concepts for raster-scan displays. If you are already familiar with how CRTs work, you may skip this section. Most of the information here is not required for emulation, but serves as reference material.

The Cathode Ray Tube

The main displays for the IBM PC were cathode-ray tube (CRT) monitors and television sets.

A cathode is a negatively-charged electrode. The cathode in a CRT is specifically part of an electron gun which fires a narrow, collimated beam of electrons toward a phosphor coating on the inside of a vacuum-sealed glass tube. The phosphor glows when struck by the electron beam, emitting light visible from the outer side of the glass, which faces the user.

The electron beam can be deflected (moved around) by magnets, since electrons have a charge and will react to a magnetic field. Electromagnets called deflection coils are used to precisely deflect the electron beam. A set of deflection coils is packaged together inside a deflection yoke, which is mounted to the back side or neck of the CRT.

CRT vertical deflection (Click to zoom)

Vector Displays

Some CRTs could use a deflection yoke to move the beam around in arbitrary directions to draw figures on the screen precisely - these were called vector displays. You may be familiar with the more famous examples used in early arcade games like Asteroids or the Vectrex video game console.

Raster Displays

Most, if not all home computer displays were raster displays. In a raster display, the electron beam is deflected on two axes at different rates. The beam moves very quickly in the horizontal direction across the screen in a succession of lines called scanlines, usually starting in the upper-left corner. At the same time, the beam is deflected downwards more slowly from the top to the bottom of the screen.

As each scanline is drawn out, the video signal is modulated - in the simplest scenario, it is simply turned off and on. This divides each scanline into individual pixel elements or pixels.

When the electron beam reaches the right side of the screen, horizontal flyback occurs, during which the electron beam is rapidly returned to the left side of the screen. The continuing vertical deflection ensures that the beam arrives at the left side slightly lower down on the screen than the previous scanline. In this manner the entire screen can be drawn, line by line, until the bottom of the screen is reached.

CRT horizontal scanout (Click to zoom)

If unaccounted for, the continuous vertical deflection would cause the image to be rotated slightly, with each scanline ending slightly lower down on the screen from where it started. To counteract this, the entire deflection yoke is mounted with a slight counter-rotation to ensure scanlines remain level.

When the beam has reached the bottom of the screen, vertical retrace occurs, as the electron beam returns to the top of the screen again, and the process repeats. This frequency at which this process occurs is called the vertical refresh frequency, and may be anywhere from 50Hz to 70Hz or more, depending on the adapter and monitor. Horizontal deflection continues throughout vertical flyback - if the beam were left on, it would be seen to ping-pong off the sides of the screen as it returned to the top. Simplified diagrams will often only show the beam moving in a direct diagonal path from one corner to the other.

CRT vertical flyback (Click to zoom)

Phosphor Decay

The phosphors on the screen are only fully lit during the period in which the electron beam is directly illuminating them, after which they immediately begin to fade. Different phosphors fade more slowly than others — the phosphors used in older monochrome monitors were long persistence phosphors, meaning they faded slowly enough that scrolling text could leave a smeary after-image or trail on the screen. The long persistence phosphors on monochrome displays made up for slower refresh rates. On color displays, fast-responding phosphors were preferred.

To a high speed camera, a CRT will look like a bright line trailed by a fading image, however a quirk of human perception called persistence of vision means that we perceive the display as having a fixed, steady image. That said, many people experience eye strain using monitors with lower refresh rates.

Color

The previous descriptions and diagrams have shown a monochrome CRT. A color CRT operates in a similar way, but with three electron beams and three sets of phosphors, one for each of the additive primary colors red, green, and blue. The individual beams are guided to their corresponding phosphors through one of several possible mechanisms, most commonly either an shadow mask or aperture grille.

Video Synchronization

A video card emits two synchronization signals, which are represented as pulses of either positive or negative polarity, depending on the current display adapter and mode. These pulses signal to the monitor the video card’s intent that a horizontal or vertical flyback be performed. These are called HSYNC and VSYNC, respectively. Most monitors, in order to protect themselves from honoring invalid or harmful synchronization frequencies, maintain one or more Phase Locked Loops (PLLs), usually implemented via some sort of sync controller IC. This allows the monitor to adapt — or sync — to a range of horizontal and vertical refresh frequencies that it can safely support, while ignoring sync signals that fall outside that range. The monitor’s PLL will cause horizontal or vertical flyback to occur when necessary, regardless of synchronization. That said, some models of monitor lack at least one PLL — such as the IBM 5151 — and can be damaged in the event that the video card sends invalid horizontal synchronization signals.

In general, the monitor’s electron beam cannot be frozen or held in place by the host computer failing to send synchronization pulses. It is constantly moving - if it is not, something has gone very wrong. For most monitors, if the card does not send synchronization signals, the monitor will trigger flyback on its own.

When a monitor fails to achieve vertical synchronization, the picture is typically seen to scroll vertically (and often rapidly) across the screen, a phenomenon called rolling. This is caused by the monitor’s PLL-driven vertical flyback being out of phase with the video signal’s VSYNC pulses. Physical knobs, like the vhold knob, are sometimes provided to assist in adjustment in this case.

When a monitor loses horizontal synchronization, the effect on the picture is much more dramatic, with the image completely scrambled instead of scrolling.

Digital vs. Analog

Video signals can often be described as digital or analog. The digital video signals of the 1980’s were not like those of today. When we talk about a digital video signal in the context of the original PC, it simply refers to TTL-level output on dedicated color and intensity pins. Video cards could sometimes emit both digital and analog signals. The DE-9 connector on MDA, CGA, and EGA cards carries a digital video signal - on the CGA, this signal is converted to an analog composite signal on the card’s composite output jack.

The VGA card introduced analog video to the PC. The VGA’s analog signal allowed a wider range of colors to be displayed without a drastic increase in pin count, by modulating voltage on each pin dedicated to the primary colors instead of relying on discrete intensity pins like with CGA and EGA.

Light Pens

The operation of raster displays allows for a unique and conceptually simple input device to be constructed. A light pen is constructed of a lens, photodiode, and filtering circuitry. When a light pen is held to the surface of a CRT, the photodiode within the tip detects the passing of the electron beam directly beneath it, causing a pulse or strobe signal to be generated. The position of the pen can be calculated on the horizontal axis by the time elapsed since the last HSYNC, and on the vertical axis by counting each scanline. A light pen often had a switch at the tip of the pen that would be pressed when held against the screen to initiate a drawing operation, separate from cursor movement.

Emulation Considerations

It’s not necessary to emulate the way a monitor scans out the screen to emulate the PC, although monitor emulation (emulating the PLLs and synchronization performed by a real monitor) can produce satisfying effects like screen bounce on mode changes. Knowledge of how horizontal and vertical sync pulses work, as well as horizontal and vertical refresh timings, are important for emulating cards such as the EGA and VGA which contain self-tests in their corresponding BIOS ROMs that test for proper operation of these signals.

Terminology

• pixel: - (Picture Element) This is usually the smallest addressable element of a raster display, determined by the capabilities of the display and display adapter.
• hdot: - (Horizontal dot) This is essentially the time-based unit equivalent to a pixel, but a pixel need not be drawn during every hdot.
• dot clock: - The frequency at which the video card produces pixels. By slowing down the dot clock, the effective horizontal resolution of a card can be decreased, making each pixel wider. The display timings of the card must be reconfigured to account for this.
• horizontal blanking period: - The period in which the electron beam is turned off at the left and right edges of the screen or beyond.
• vertical blanking period: - The period in which the display is turned off at the top and bottom edges of the screen or beyond.
• horizontal retrace: - The period in which the electron beam is being moved from the right side of the screen to the left side. Occurs during the horizontal blanking period. Also called a horizontal flyback.
• vertical retrace: - The period in which the electron beam is being moved from the bottom-right of the screen to the top-left side. Occurs during the vertical blanking period. Also called a vertical flyback.
• horizontal front porch: - The period of the horizontal blanking period immediately before the horizontal retrace period.
• horizontal back porch: - The period of the horizontal blanking period immediately after the horizontal retrace period.
• vertical front porch: - The period of the vertical blanking period immediately before the vertical retrace period.
• vertical back porch: - The period of the vertical blanking period immediately after the vertical retrace period.
• HSYNC: - A signal the display adapter sends to the monitor to initiate the horizontal retrace period.
• VSYNC: - A signal the display adapter sends to the monitor to initiate the vertical retrace period.
• horizontal refresh rate: - The frequency at which the monitor displays an entire scanline, ending in an hsync. Expressed in kHz.
• vertical refresh rate: - The frequency at which the monitor displays an entire frame, ending in a vsync. Expressed in Hz.
• overscan:
  • On analog television sets, the overscan is part of the video signal that may be hidden by the display’s bezels.
  • On digital computer monitors, ‘overscan’ typically refers to the part of the video signal which lies outside of the region where addressable pixels are displayed, which may lie partially within the borders of the monitor’s bezels, and partially outside it. The overscan can often be set to a particular color, depending on the adapter.

Primary References:

• (cosmodoc.org) People Don’t Like Electrons Shooting At Their Face

The Motorola MC6845

The Motorola MC6845

The Motorola MC6845 is a Cathode Ray Tube Controller (CRTC). Its primary purpose is to generate video memory addresses and video synchronization signals as part of a larger raster display system. It contains a number of registers that together define a specific video frame geometry, and a number of counters that are incremented or decremented while being compared against the values stored in the register file. These comparisons happen continuously, via circuits attached to the registers themselves called coincidence circuits. That’s just a fancy name for a simple equality comparator.

You can see the coincidence circuits in the image below as the green boxes that sit above most of the pink registers.

Motorola MC6845 Annotated Die Photo (Click to zoom)

When certain counters coincide (become equal with) certain registers, various logic circuits may be triggered. For example, when the counter that holds the current character-column position becomes equal with the register that holds the total number of characters to be displayed, the MC6845 will indicate via an external pin that the display area has ended for the particular line. In this manner the MC6845 can produce the display timing signals corresponding to the configured frame geometry.

As part of a video card or other display system, these signals trigger further logic on the card itself - for example, the DE or Display Enable pin, might be tied to logic that controls whether the video card outputs graphics data or emits a solid black color. The MC6845’s MA pins will typically be used to address the video card’s video memory.

Character Cell Logic

The MC6845 is fundamentally designed to handle character-based or text mode displays. It assumes that your characters will all be of the same width and height, but they do not need to have exactly equal width and height. The MC6845 can handle characters up to 32 lines tall. In most implementations, a line from the MC6845’s perspective is equal to a scanline on the monitor.

The rectangular bitmaps that define how characters appear on screen are called character glyphs. The MC6845 does not define any margins or spacing between glyphs - the requisite spacing must be encoded into the glyph bitmaps themselves. On the IBM PC, there is typically one pixel of spacing between each character, horizontally and vertically, but in certain circumstances a video card may override this.

Here is a hypothetical example of a row of 6x8 character glyphs:

The MC6845 has no concept of how wide your character glyphs actually are. Most video standards for the PC will define a character that is either 8 or 9 pixels wide, usually producing a horizontal display resolution of 640 or 720 pixels when configured for an 80-column display. But you could have 64 pixel wide characters, or 4096 - the only limits are practicality and memory bandwidth.

If we think about it, the MC6845 leaves us a lot of leeway to provide our own definition of what a ‘character’ even is. We could just as easily use the MC6845 to drive an array of LEDs. It is exactly this sort of flexible representation that allowed graphics vendors using the MC6845 to implement graphics modes on what was a fundamentally character-based chip. To learn more about how that was done, you’ll need to read a chapter that discusses a specific card like the IBM CGA.

The MC6845 has to draw every row of characters several times - as many times as the character height is defined in lines. Each pass through a row draws the subsequent row of pixels of each character glyph. This is controlled by an internal counter C9 (Vertical Line Counter), the contents of which are emitted on the CRTC’s RA pins which in turn can be used to address an external character (font) ROM.

Clocking the MC6845

The MC6845 receives a clock called the character clock which indicates how fast characters should go by on the screen, since that is what the MC6845 is managing. This is typically produced by taking the dot clock input of the card and dividing it by the current character width.

For every new clock edge of the character clock, the MC6845 produces a memory address on its 14 MA address pins.

Memory Address Generation

The MC6845’s address pins provide the address of the character that should be displayed at roughly that instant (ignoring rasterization latency). On each character clock, the internal memory address, a counter called VMA, is either incremented by one, reset, or set to a latched value, depending.

The address emitted by the MC6845 may not be a literal byte address. As discussed above, a character address can be interpreted liberally. In IBM CGA text mode, each character cell is a 16-bit value: pairs of ASCII character codes and CGA attribute bytes. The address may be further manipulated in other ways, sometimes using the RA counter - a common trick to create graphics modes.

MC6845 Registers

The MC6845’s register numbers are frequently given in either decimal or hexadecimal. Motorola’s own references use decimal, so that is what we will use here.

The MC6845 has two IO ports - an address port, and a data port. One should first select a register via the address port, which is done by holding the RS pin low. This is an electrical detail you are unlikely to need to emulate - the card on which the MC6845 has been included will decode a separate IO address for the MC6845’s address and data register. See the chapter for the specific card you are emulating. From the CGA onwards, the CRTC registers are at 3D4h and 3D5h.

The address register, being 5 bits wide, will happily hold any value from 0-31, meaning an invalid selection may be stored. In this scenario, writing to the data register has no effect, and reading from the data register is ultimately implementation-specific but likely to return either 0x00 or 0xFF. The chapter for a specific card may have more details.

Most of the registers simply contain integer values, but pay close attention to their bit lengths, and perform the appropriate masking when writing to them.

Two exceptions to this rule are R8, which contains two flags relating to interlaced video, and R10, which contains two additional bits that control cursor blinking. Their formats are given here.

Interlace Mode and Skew

Cursor Start Register

Don’t worry about the meaning of the fields in these registers just yet. The register definitions are provided here for completeness with the register table reference.

MC6845 Counters

The table above shows the various counter units on the MC6845. They will be largely referred to here by their names in the Name column. If you read the source for other emulators, you may encounter names given in the Description column. The new names for these counters come from the Amstrad CPC CRTC Compendium.

Latches and Flags

The MC6845 has an important latch which is referred to as VMA' or VMA Prime. VMA' can be loaded with the value of the VMA counter, and the VMA counter can be loaded with either VMA' or the contents of the Start Address registers, R12 and R13.

You can see the VMA' latch as the tall vertical section immediately to the right of the VMA counter in the die photo above.

Besides the VMA' latch, there are various bits of state that the MC6845 can keep as flags. These include a last_line flag.

Defining a Frame

A frame is a single image displayed on a CRT monitor, typically delineated by VSYNC pulses. See Display Concepts if this isn’t already a familiar concept. The role of the MC6845 is managing the size and timings that define a single frame. The MC6845’s registers define these parameters, and its counters are used to actually play out said timings - a process I will refer to as scanout.

The most important concept to grasp when understanding how the MC6845 defines a frame is that it is not just defining the position and size of visible elements, but also timings for invisible events such as horizontal and vertical sync periods. It can be helpful to think of a MC6845 frame as a two dimensional time chart, or field diagram - this allows us to map areas where the raster beam may be moving around as simply a region of time. This book will often discuss this imaginary display field, and you may need to frequently refer back to this diagram for reference.

The diagram below demonstrates the typical parameters used to implement the standard 80x25 text mode display on an IBM CGA card.

The CRTC Display Field Diagram (Click to zoom)

Frame Extents

The two-dimensional extents of the display field are defined by R0 and R4. They represent the width and height of the field, respectively, minus one.

The extents of the display area are given by R1 and R6. These contain the exact width and height of the display area. In the diagram above, you can see they are programmed for 80 and 25, as expected.

The other parameters set up the positions (and sizes, where applicable) of the horizontal and vertical blanking/sync periods, which overlap each other, as several horizontal syncs will occur during vertical blanking.

The rest of the screen is a sort of no-man’s land we call the overscan. Some video cards will let you emit a solid color here. Not all cards have such large overscan areas.

It may not be possible to produce a screen using just a multiple of your character height that satisfies display requirements, such as NTSC’s specification of 262 scanlines. For example, a field of 32 rows (R4 == 31), with 8 scanline tall characters, only produces 256 scanlines. This may cause trouble with your monitor’s vertical synchronization circuitry. Thus the register R5 is provided to pad out the end of the frame by the indicated number of scanlines - in the above case, 6, until a full 262 scanlines are emitted.

MC6845 Outputs

While still referring to the diagram, note that the MC6845 will raise its HS pin when it is within the blue hblank period. It will raise its VS pin when it is in the lighter blue vblank period. Both pins will be asserted when these periods intersect.

While the MC6845 is scanning out the region defined by R1 and R6, it will assert its DE (Display Enable) pin, which should drive rasterization of text or graphics by the attached display system.

Scanning out a Frame

The process of scanning out the frame or display field may be considered to start in the upper left corner of the display area.

C0 and C4, our horizontal and vertical character counters will both be 0. C9, our vertical line counter - indicating what row of a character we are drawing - will also be 0.

At the beginning of a frame, the MC6845 performs Start-Of-Frame Management.

Start-Of-Frame Management

The VMA counter is loaded with the 14-bit start address taken from the R12 and R13 start address registers. The VMA' latch is loaded with the same address at this time. Note that as VMA counts, VMA' retains the same value unless updated by some other event.

We will start in the active display area, so DE will be high.

Scanning out a Row

Every character clock, a number of comparisons are made that trigger various state changes. It may be helpful to think of these as occurring before the increment of any counter.

• If C0 == R1, we leave the active display area and enter the right overscan period.
• If C0 == R2, we enter the horizontal sync period, which we will gloss over for the moment.
• If C0 == R0, we have reached the far end of the display field.
  • If C9 == R9, we are on the last scanline of a row, in which case we enter End-Of-Row Management.
  • Otherwise, C9 is incremented, VMA is updated with VMA' (to reset the memory address to the start of the row again), and the process repeats.

Each row is scanned out R9 + 1 times. In our 80x25 text mode example, we can see that R9 is 7. Therefore each row will consist of 8 scanlines.

Frame Scanout, Visualized

The logic above for scanning out rows is repeated. During End-Of-Row Management, C4 is incremented. When C4 == R4 we have reached the end of the screen. At this point, if R5 is nonzero, C5 will be initialized with R5 and the MC6845 will start scanning out R5 scanlines in the Vertical Total Adjust Period. When this has elapsed, or if R5 was zero, the frame ends and a new frame immediately begins.

You can see an animation of the full frame scanout process below, with certain internal counters visualized.

Cursor Management

The MC6845 has a hardware cursor, with a dedicated CURSOR pin. This pin is typically active during character clocks when the current VMA matches the value configured by the Cursor Address Registers (R14 & R15) and the current value of C9 is within the range defined by the Cursor Start (R10) and Cursor End (R11) registers.

The CURSOR signal will be suppressed for several frames for the same memory location as the cursor blinks off, unless blinking has been disabled.

In a normal scenario, Cursor Start is programmed for a value less than Cursor End, and the cursor is drawn from the scanline represented by Cursor Start up to and including the scanline represented by Cursor End. If Cursor Start and Cursor End are equal, the cursor will be drawn for a single scanline.

The cursor on the IBM PC is usually two scanlines tall.

The cursor is typically configured to appear at the bottom of a character cell, but nothing prevents you from placing it at the top:

Hiding the Cursor

There are three primary ways of hiding the cursor on a MC6845-based video card:

• You can set the cursor address to a memory address outside of the current display area.
• You can set the Cursor Start register to a value greater than R9.
• You can set the blink bits to 01 in the Cursor Start register.

Cursor Tricks

Some odd things happen when you start playing around with non-standard configurations of cursor start and end.

If you set the value of Cursor End > R9, then a full-block cursor is created.

More unexpectedly, if you configure Cursor End < Cursor Start < R9, you can get a “split” cursor:

The explanation for this behavior is really quite simple. The MC6845 has an internal flag that we will call Cursor Active (CA). The cursor is not evaluated per character cell, it is evaluated per scanline. When we reach the end of each scanline while scanning out a row, the MC6845 checks if the new row scanline matches the value in Cursor Start. If it does, the CA flag is turned on. In a similar fashion, if the outgoing row scanline matches Cursor End, the CA flag is turned off.

What is important to understand here is that these comparisons against the cursor start and end are all that controls this global cursor flag. It is not reset upon VSYNC, or new frames.

Let’s reexamine the case of the solid block cursor. By configuring Cursor End > R9, we ensure that the comparison that would otherwise turn the cursor off, can never be true. Therefore the CA flag is turned on, and stays on permanently. However, the cursor is only actually visible in the bounds of a single character cell when VMA matches the Cursor Address.

By making Cursor End < Cursor Start it should now be clear that this reverses or “inverts” the cursor definition. Instead of turning on and then off within a character row, it turns off and then on - remaining on as we proceed to the next row. In this sense, the cursor is now spanning across two rows at a time - it isn’t “split” at all, it just appears that way given the limited aperture of a single character cell.

Ultimately, cursor visibility is a combination of CA AND VMA == Cursor Address AND NOT blink.

Important

The CA flag is not updated during the vertical total adjust period.

Interlaced Mode

For most of the PC’s history, the MC6845’s interlaced mode was not used. On the IBM CGA, IBM even took measures to make sure it was nonfunctional. Only recently have demoscene coders started exploring the use of interlaced mode for various effects. This section will be expanded in the future.

Light Pen

The MC6845 has basic support for light pens. The chip’s physical LPSTB or light pen strobe pin is a positive-edge-triggered input, that causes the current VMA to be written to R16 and R17. This is an asynchronous input signal that can occur any time, so presents a bit of challenge for an otherwise synchronous chip. The exact electrical details are not particularly important. Heed Motorola’s warning that the address ultimately latched may be some character clocks distant from when the strobe actually fired. In experience, on an IBM CGA card, this produces a cursor offset of 5-6 character clocks before calibration.

Most light pen-supporting programs and light pen drivers will have calibration routines to offset this delay.

The LPSTB input is not latched - every time there is a rising edge a new address will overwrite the values of R16 and R17. If this is not desired, a card maker may place a resettable flip-flop in between the light pen’s strobe input and the MC6845 LPSTB pin. Since most light pen strobe inputs are active-low, an inverter is typically employed as well.

Datasheet

• (archive.org) Motorola MC6845

Primary References

• (shaker.logonsystem.eu) The Amstrad CPC CRTC Compendium V1.9

Additional Watching

• (youtube.com) Visiting Area 5150

Monochrome Display Adapter (MDA)

The IBM Monochrome Display Adapter (MDA) was one of the first video adapters available for the IBM PC, along with the IBM Color Graphics Adapter and the third-party Hercules video adapter.

Important

The MDA is built around the Motorola MC6845 CRTC. Read that chapter first for a basic understanding of how the CRTC is used to define frame geometry and draw the screen.

At a Glance

The MDA was intended for use with the IBM 5151 Personal Computer Display. This monitor plugged into the back of the PC’s power supply and turned on and off with the system. The MDA card itself was only capable of displaying text mode, but the monitor itself could display graphics, which cards like the Hercules Graphics Adapter took advantage of to provide a tempting upgrade for 5151 owners.

The MDA has 4KiB of DRAM dedicated to video memory — enough to hold a single 80x25 screen’s worth of text. It also has an 8KiB font ROM that holds bit patterns for drawing text glyphs.

The MDA’s 4KiB of DRAM at segment B000:0 is incompletely decoded, causing eight mirrors of video memory from B000:0 through B700:FFFF. This ends at the CGA’s memory address of B8000. Along with the different base IO address, this allowed one to install both an MDA card and a CGA card in the same system for an early dual-monitor setup.

The MDA has no on-board video BIOS or expansion ROM. All PC-compatible BIOS implementations must therefore know how to identify, initialize and operate an MDA card in order to provide standard int 10h services.

In text mode, the MDA card was capable of outputting 3 grayscale shades and black, using two output pins of its DE-9 video connector. Some early MDA cards could be coerced into showing 16 colors.¹

The MDA contains a 16.257MHz crystal. The refresh rate is approximately 50Hz.

The IBM MDA card included a parallel printer port. See that section for more details.

Note

* Incomplete decoding of the CRTC registers means the two CRTC ports are repeated four times. Some software titles may rely on these alternate port numbers.

MDA Character Glyphs (Standard Font)

The standard MDA character glyphs are shown below.

A visualization of the character font ROM is shown below, with bytes reversed and wrapping vertically to fit into a square image. The first half of the ROM is dedicated to the MDA’s 8x14 font, which is encoded into 8x16 cells for alignment. Each cell is split into two 8x8 parts within the ROM due to addressing logic.

The same character ROM image is used for both MDA and CGA, so the CGA fonts follow the MDA font in the latter half of the ROM.

The MDA/CGA character font ROM (byte-reversed)

The character font ROM is not accessible from the host PC. It can only be read by the MDA itself.

Box Drawing Characters

Character codes C0h—DFh receive special treatment. When one of these characters is being rasterized, the eighth column is repeated to form the ninth column on the display. This allows the box drawing characters to connect seamlessly together across a 9-pixel character cell.

MDA box drawing character rendering

Note that B0h—B2h do not receive this treatment, so areas shaded with these characters will still have one pixel gaps between each character glyph.

The MDA Registers

Mode Control Register

Caution

IBM warns that the first thing that must be done to initialize the MDA is to set bit 0 of the mode control register to 1.

Bit 0 of the mode control register selects the MDA’s dot clock. When set to 1, the onboard 16.257MHz crystal is used. If set to 0, the clock is taken from an unpopulated pad. If the MDA’s video memory is accessed while this bit is 0, the MDA card will fail to drive the IO_CH_READY pin on the ISA bus high, and the CPU will hang. It is unclear what IBM’s original intent for implementing this was, but perhaps they were simply keeping their options open for a future variant that supported additional resolutions and would have subsequently required a second clock source.

Status Register

The MDA’s status register is very different from the CGA. The first bit reflects the HS pin from the 6845, delayed by one character clock. This differs from the CGA, which reports the inverted DE pin from the 6845.

The MDA also lacks the vertical sync status bit. Instead, it has a type of video mux bit, LVIDEO. Querying bit 3 can test if an active pixel of any “color” other than black is being output. The IBM BIOS primarily uses this as a test during POST to ensure that the card is functioning.

Tip

When writing MDA emulation, implementing the LVIDEO bit may seem daunting. It is generally sufficient to set the latch if any pixel was output in the previous character clock (or even scanline) instead of requiring pixel-perfect accuracy. The IBM BIOS draws a row of solid block characters and tests that the bit is set immediately at the start of the frame. It is unknown if any software besides the BIOS POST relies on this bit for proper functionality.

Light Pen

The very earliest models of the MDA card include a header to attach a light pen, similar to the CGA. This was removed on all subsequent versions of the card — the entire footprint was removed, not just left unpopulated, and in addition, the strobe signal to the 6845 and the two status bits for light pen operation were also disconnected and will always return 0.

The P39 phosphors used in most monochrome displays were incompatible with early light pens for the PC, which may have influenced IBM’s decision to remove light pen support from the MDA.

Display Timings

The MDA has a 16.257MHz crystal.

We can calculate the typical display field of the MDA from its normal CRTC parameters:

$$H_{\text{total}} = (R0 + 1) \times 9 = (97 + 1) \times 9 = 882$$

$$V_{\text{total}} = (R4 + 1) \times (R9 + 1) + R5 = (25 + 1) \times 14 + 6 = 370$$

$$\text{display field} = 882 \times 370$$

The horizontal and vertical refresh rates can then be derived:

$$f_{hsync} = \frac{16{,}257{,}000}{882} = 18.43 \text{ kHz}$$

$$f_{refresh} = \frac{16{,}257{,}000}{882 \times 370} = 49.82 \text{ Hz}$$

BIOS Video Mode

The MDA typically uses standard int10h video mode 7.

CRTC Parameters

For the MDA’s standard text mode, the MC6845 CRTC needs to be configured with the correct parameters for registers R0-R11. The standard CRTC parameters are given below.

Primary References

• (seasip.org) Monochrome Display Adapter: Notes
• (minuszerodegress.net) IBM Monochrome Display and Printer Adapter (MDA)

1. VCFed forum thread, Why did IBM create color MDA and just abandoned it?, April 2025. ↩

The IBM Color Graphics Adapter

The IBM Color Graphics Adapter (CGA) was one of the first video adapters available for the IBM PC, along with the IBM Monochrome Display Adapter and the third-party Hercules video adapter. It is perhaps the classic video card that comes to mind when people think of the IBM PC.

Important

Like the MDA, the CGA is built around the Motorola MC6845 CRTC. Read that chapter first for a basic understanding of how the CRTC is used to define frame geometry and draw the screen.

At a Glance

The CGA could be connected to a regular North American television set via its composite output connector, although most sets of the time would require an RF modulator to do so. A DE-9 connector provided a digital RGBI signal that could be used with an IBM 5153 Color Display. IBM left owners of the CGA waiting a bit for that particular monitor - it was only released in 1983, two years after the CGA’s debut.

The CGA has 16KiB of DRAM dedicated to video memory, and an 8KiB font ROM that holds bit patterns for drawing text glyphs.

The CGA’s 16KiB of DRAM at segment B800:0 is incompletely decoded, causing a mirror of video memory that begins at BC00:0. You can use this mirroring to your advantage in certain circumstances.

The CGA has no on-board video BIOS or expansion ROM. All PC-compatible BIOS implementations must therefore know how to identify, initialize and operate a CGA card in order to provide standard int 10h services.

In text mode, the CGA card was capable of outputting 16 colors. In graphics mode, it was limited to 3 palettes of 3 fixed colors each, with a selectable background color. The CGA also had a high-resolution mode, with a single, selectable foreground color on black.

The CGA’s standard display resolution is 640x200 at a refresh rate of approximately 60Hz.

The CGA maps the MC6845’s two external registers at address 03D4h for the address register and 03D5h for the data register.

Note

* Incomplete decoding of the CRTC registers means the two CRTC ports are repeated four times. At least one known game, Prohibition, relies on this incomplete decoding.

Operational Modes

The CGA has three primary modes of operation: text mode, medium-resolution graphics mode, and high-resolution graphics mode. A brief overview of each mode follows; each will be covered in greater depth later on.

Text Mode

In text mode, the screen is constructed from a grid of character glyphs. IBM called this mode Alphanumeric Mode (A/N) in documentation.

The IBM PC boots into text mode, either in 40-column or 80-column mode depending on how certain DIP switches are set. 40-column mode makes each glyph twice as wide due to a halved dot clock. It was primarily intended for use with television sets, on which 80-column text was difficult to read. Various tweaked text modes were derived by inventive coders over the years that provided a different number of rows and columns, so these extents are not set in stone.

The standard text modes have black and white and color mode variants, although this typically only controls color when using the composite output. The background and foreground color of each character cell can be controlled via attribute bytes.

In text mode, a blinking, hardware cursor is usually shown indicating where the user can type - or if the programmer doesn’t bother hiding it, where the screen was last updated.

CGA 80-column text mode - MS-DOS 5.0 EDIT

Medium Resolution Graphics Mode

In medium-resolution graphics mode, the screen is composed of a 320x200 grid of pixels. IBM called graphics mode All-Points-Addressable (APA) mode.

This is perhaps the most famous mode of the CGA, especially its cyan-magenta-white palette as seen in games like Alley Cat.

In this mode, three basic ‘palettes’ are available, two of which are notorious for being ugly. These are not actually palettes as they are typically understood - more on that below. What might be thought of as index 0, specifies the background color. The background color is usually black, but can actually be chosen from any of the CGA’s 16 possible colors. Careful use of this “extra” palette entry can create interesting effects that also extend into the borders (or overscan) of the screen. Games could use this color to indicate status, such as flashing it red to indicate your player character had taken damage. The color would create a frame around the addressable display area that could have a surprisingly dramatic effect.

The cursor is disabled in this mode.

CGA 320x200 graphics mode - Alley Cat by Bill Williams

High Resolution Graphics Mode

This mode provides a very stretched 640x200 monochromatic graphics mode. The foreground color used to draw can be selected from any of the 16 available CGA colors, but the background cannot be changed from black. This mode can be used, with the color burst turned on, to enable 16-color composite artifact color modes.

The cursor is disabled in this mode.

CGA 640x200 graphics mode - SHUTTLE.BAS

The RGBI Color Gamut

The CGA has a digital DE-9 output connector. To produce color, the CGA controls four output pins — one for each of the primary colors: Red, Green, and Blue, along with an “intensity” signal. Four bits give us \(2^4\) or 16 possible colors. The intensity pin provides a repeat of the first eight colors, but brighter.

The odd duck out here is non-intensified yellow, which has been conspicuously darkened to become brown. This was a deliberate decision by IBM, who perhaps found the rather sickly dim yellow unpleasant, or at least believed that a brown color would be more useful. Speculation abounds, but the interesting thing to note is that the conversion circuit to turn yellow into brown is not actually present on the CGA at all - the circuitry is within the IBM 5153 Color Display itself, and third party PC-compatible monitor manufacturers largely followed suit. You may see the original yellow color instead on some non-CGA compatible monitors.

In text mode, any of these sixteen colors can be referenced within a character attribute byte.

In graphics modes, the CGA operates in what we might term direct color mode, where the bits set in video memory directly influence the Red and Green output pins.

The CGA only has one true palette register as we typically define one, as in a register that holds an arbitrary color. It is the background/overscan color field in the Color Control Register.

The CGA Registers

Mode Control Register

The CGA Mode Register generates the main control signals that drive the logic of the card. Most descriptions of what these bits do, even in IBM’s own references, only give you an approximation of their actual function. To enter a standard graphics mode, besides reprogramming the CRTC, the correct mode bits must be set.

• The HIRES bit enables the 14.31818MHz dot clock and high-resolution character clock for 80-column text mode. It should not be used in conjunction with the GFX or HIRES_GFX bits.
• The GFX bit enables graphics mode, and triggers replacement of memory address A13 with RA0; a further explanation is given in the medium-resolution graphics section.
• The B/W bit disables the composite color burst. It will produce a black and white or grayscale image on a composite monitor or television set. RGBI displays such as the IBM 5153 Color Display will still display color as normal with this bit set, although a third graphics palette can be selected via this bit in medium-resolution graphics mode.
• The VIDEO bit is described by IBM as disabling the video signal - this is not accurate. This bit pulls low the \(\overline{\mathrm{CLR}}\) pins of the CGA’s graphics serializers, U7 and U8. The effect of this is the appearance that all video memory contains 0. This often does result in a black screen, but where conditions allow display of color, such as the border/overscan color being set, color will still be displayed.
• The HIRES_GFX bit enables logic on the card to rapidly enable and disable the CGA’s color multiplexers. This bit should not be used in conjunction with HIRES or the text on the screen will become corrupted.

There are several combinations of mode bits that are invalid, and may have strange and interesting effects.

The color control (or color select) register contains the CGA’s only real color palette entry - an RGBI color may be specified that provides the background/overscan color. This color definition has three distinct use cases - in text mode, it provides the border/overscan color. In medium-resolution graphics mode, it provides the color to use when a pair of bits are both 0, in addition to providing the border/overscan color. In high-resolution graphics mode, it controls the color used to represent 1 pixels. Note that I have deliberately avoided calling this the “foreground color”. See the section on high-resolution graphics mode for the reason why.

The overscan or border is an infamously large area around the visible or active display area of the IBM CGA. Here is a fairly accurate representation of its extents on an IBM 5153 monitor. If you look closely, you can even see the command that has just set the overscan color to cyan:

The CGA overscan/border region, set to cyan via the CC register (Click to Zoom)

The other two bits in the color control register, PAL_I and PAL_B, provide the intensity and blue components of all colors generated in medium-resolution graphics mode. They effectively select from four different color gamuts.

The CGA status register contains two essential bits for synchronizing graphics with the display. Bit 0, \(\overline{\mathrm{DE}}\), is the inverted DE pin from MC6845. Therefore it will be 0 when the MC6845 is scanning across the active display area, when the native DE pin is 1.

Bit 3, VR, is the non-inverted VS pin from MC6845 latched on the next hclock. When VR is 1 we are in the MC6845’s vertical blanking period. Note that, unless some serious CRTC abuse is occurring, \(\overline{\mathrm{DE}}\) will always be 1 when VR is 1.

The CGA’s memory access and rasterization latency produces one character of display enable skew. Therefore, \(\overline{\mathrm{DE}}\) will flip to 0 one character clock before the CGA starts drawing the active display area, and will flip back to 1 one character clock before the end of the active display area is drawn.

The following diagram may help clarify the values of these two status bits at different points on the screen:

A visualization of the /DE and VR bits in the CGA Status Register (Click to Zoom)

The two other bits in the CGA status register concern themselves with light pen operation.

• The LPT bit is the state of the light pen strobe trigger. The term trigger can evoke the sense of a physical trigger or button on the light pen, but this is not the case. The light pen trigger is fired when the photodiode within the attached light pen detects light (the strobe) from the CRT raster beam. When this bit is 1, the MC6845’s light pen latch registers should contain the valid approximate position of the light pen. This bit is latched via a flip-flop on the CGA, and will remain set indefinitely unless cleared by writing any value to port 3DBh, after which a new strobe trigger may fire and a new light-pen position latched by the MC6845. The strobe trigger may be manually fired without input from the pen by writing to port 3DCh. It is possible to crudely determine the current raster position of the display with this method, but it is highly unreliable. Even so, it didn’t stop games like Jungle Hunt from using it to perform mid-frame palette swaps.

• The LPS bit is the immediate state of any switch connected to the light pen header’s switch pin. The light pen switch signal is active-low, explaining why this bit is logically reversed. This is simply the immediate state of any switch present on the light pen - this switch may be at the tip of the pen on high-quality light pens. The switch is typically used for taking actions such as initiating a drawing operation. IBM’s documentation warns us that this signal is not debounced in any way, but a high quality pen should debounce the switch for us.

Text Mode

In text mode, video memory is organized conceptually as a grid of character cells. The dimensions of this grid are directly configured on the CRTC, and are typically 80x25. Each logical cell consists of a pair of bytes in video memory, the first byte being a character code and the second byte being a character attribute.

The character code, combined with the vertical line counter of the CRTC, is used to resolve a byte contained in the CGA’s font ROM representing 8 pixels (or span) of a character glyph. You can see the standard CGA character glyphs below.

CGA Character Glyphs (Standard Font)

The standard CGA font implements IBM Code Page 437. The vast majority of CGA cards were shipped with this font ROM, however there were variants sold for the international market that contained alternate code pages.¹

The CGA ostensibly provides a second “thin” font selectable by a jumper, but on most examples of the IBM CGA this jumper is not populated on the PCB, requiring some soldering to actually utilize. Why IBM changed their mind about making this font user-selectable is up for debate. However, an emulator author can certainly choose to make the font more easily selectable.

A visualization of the character font ROM is shown below, with bytes reversed and wrapping vertically to fit into a square image. The first half of the ROM is dedicated to the MDA’s 8x14 font, each glyph of which is split into two parts. The latter half of the ROM consists of the ‘hidden’ thin font, followed by the standard CGA font.

The MDA/CGA character font ROM (byte-reversed)

The character font ROM is not accessible from the host PC. It can only be read by the CGA itself. int 10h services include routines for drawing text in graphics modes - to accomplish this, a copy of the standard CGA font is present in the IBM PC BIOS as well.

Character Attribute Byte