Intel 8237 DMA Controller
The Intel 8237 DMA (Direct Memory Access) Controller enables efficient data transfers between memory and I/O devices without CPU intervention. In the IBM PC, it coordinates data transfer to and from floppy and hard drives, as well as performing DRAM refresh cycles.
Overview
The 8237 provides four independent DMA channels, each capable of transferring data between memory and peripherals. In theory, the 8237 is capable of performing memory-to-memory transfers as well, but its implementation in the IBM PC prevents it from doing so.
IBM PC DMA Configuration
| Channel | Purpose | Device |
|---|---|---|
| 0 | Memory Refresh | DRAM |
| 1 | Unused | - |
| 2 | Floppy Disk | FDC |
| 3 | Hard Disk* | HDC |
Note: Not all hard disk controllers use DMA. Notably, most models of the XTIDE do not.
Hardware Interface
I/O Ports (8237A-5)
| Port | Register | Access |
|---|---|---|
| 0x00 | Channel 0 Address | R/W |
| 0x01 | Channel 0 Count | R/W |
| 0x02 | Channel 1 Address | R/W |
| 0x03 | Channel 1 Count | R/W |
| 0x04 | Channel 2 Address | R/W |
| 0x05 | Channel 2 Count | R/W |
| 0x06 | Channel 3 Address | R/W |
| 0x07 | Channel 3 Count | R/W |
| 0x08 | Status Register | R |
| 0x08 | Command Register | W |
| 0x09 | Request Register | W |
| 0x0A | Mask Register | W |
| 0x0B | Mode Register | W |
| 0x0C | Clear Flip-Flop | W |
| 0x0D | Master Clear | W |
| 0x0E | Clear Mask Register | W |
| 0x0F | Write All Mask Bits | W |
Page Registers
The DMA page registers are not part of the 8237 itself, but are implemented on the motherboard. They are provided here for convenience.
Note: The page register addresses are mapped out of order from their respective channels. Take note of the assignments.
- 0x81: Channel 2 Page Register (Address bits 16-19)
- 0x82: Channel 3 Page Register (Address bits 16-19)
- 0x83: Channel 1 Page Register (Address bits 16-19)
The IBM AT added a page register for Channel 0, but this is not implemented on the PC/XT:
- 0x87: Channel 0 Page (bits 16-19)